CSE370 Assignment 6

Distributed: Feb. 6, 1998
Due: Feb. 13, 1998

Reading:

Katz: Chapter 5, pp. 240-262, 266-269

Exercises:

1. Refer to Fig. 5.14. Show the value of each signal in this circuit when this adder adds the two numbers 0110111101011100 and 0010000110100100 with a carry in of 0.

2. The text shows how to implement a carry-lookahead adder using 4-bit stages (Fig. 5.12, 5.14). In this problem, we are going to reduce this to 2-bit stages. That is, each stage adds 2 bits instead of 4 bits. Each carry lookahead unit generates 2 carries instead of 4.
   Design a complete 8-bit carry-lookahead adder using 2-bit carry-lookahead stages. Implement this design using Synario schematics. Write a test fixture that exercises the worst-case delay path. Hand in your schematics, the test program and the resulting waveforms. (This is not as hard as it sounds. You just need to implement two block symbols and connect them together.)

3. Katz 5.25

4. Work through the TUTORIAL 3: DEVICES tutorial. This tells you how to map your ABEL program to an actual PLD (PAL).

5. Find the tutorial page USING ABEL SOURCE AS BLOCK SYMBOLS WITHIN A SCHEMATIC (at the end of the INTRODUCING ABEL-HDL tutorial). This shows you how to create a schematic block symbol from an ABEL program.

6. Write an ABEL program to implement an 8-1 multiplexor. Map this to a P16H8 PAL and print out the chip report. Now make a block symbol for your ABEL multiplexor. Use this multiplexor in a schematic to implement a comparator that compares two 2-bit numbers and asserts the output if the numbers are equal.
   Turn in a printout of the ABEL program, the chip report and compiled equations, your schematic, the test program and the resulting waveform.

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