CSE370 Assignment 3

Distributed: Jan. 16, 1998
Due: Jan. 23, 1998


Unless specifically stated otherwise, you are encouraged to discuss solutions to the homework with other students. However, you must (1) spend at least 15 minutes on each and every problem alone, before discussing it with others, and (2) write up each and every problem in your own writing, using your own words, and understand the solution fully. You may also apply the Gilligan's Island approach - work together on a problem as much as you want, but watch a full episode of Gilligan's Island before writing down the solution or entering the program on your own.

Assignments are due at the beginning of class on the assigned due date. Assignments handed in during or immediately after class will incur a 10% penalty. We will not accept assignments after we have left the classroom.


Reading:

Katz: Chapter 2, pp. 75-85, 92-102


Exercises:

  1. Katz: 2.16 b, d
  2. Katz: 2.18 c, e
  3. Katz: 2.19 b
  4. Katz: 2.20 c
  5. Katz: 2.26
  6. Katz: 2.30

  7. Laboratory assignment:
    Continue with the first Synario tutorial by working through the following topics:

  8. Laboratory assignment:
    In the previous assignment, you designed a circuit for a full adder. You should now take this circuit and turn it into a block symbol. You can then use this symbol to represent the entire circuit in your previous schematic.

    Draw a new schematic, using your full adder, to implement a 4-bit 2's complement adder. This adder has two 4-bit inputs, and one 4-bit output. (Ignore the carry out and assume there is no carry in.)
    Simulate this circuit using a test fixture that generates the following 10 test cases:

    1. 3 + 4
    2. 1 + -1
    3. 7 + -8
    4. -1 + -1
    5. 6 + 5
    6. 2 + -6
    7. -7 + 3
    8. -5 + 7
    9. 4 + 4
    10. 7 + -7
    Hand in your schematic and the results (waveform) of your simulation. It should be easy to see from your simulation that your circuit works.

    Extra Credit: Add an extra output signal for the overflow condition. Recall that there is an overflow if the carry into the sign bit is different from the carry out of the sign bit.


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