CSE370 Assignment 2

Distributed: Jan. 9, 1998
Due: Jan. 16, 1998

Unless specifically stated otherwise, you are encouraged to discuss solutions to the homework with other students. However, you must (1) spend at least 15 minutes on each and every problem alone, before discussing it with others, and (2) write up each and every problem in your own writing, using your own words, and understand the solution fully. You may also apply the Gilligan's Island approach - work together on a problem as much as you want, but watch a full episode of Gilligan's Island before writing down the solution or entering the program on your own.

Assignments are due at the beginning of class on the assigned due date. Assignments handed in during or immediately after class will incur a 10% penalty. We will not accept assignments after we have left the classroom.

Reading:

Katz: Chapter 2, pp. 64-80

Exercises:

1. Katz: 2.7 b,d
2. Katz: 2.9
3. Katz: 2.10 a,b,c
4. Katz: 2.11
5. Katz: 2.13 c
6. Katz: 2.16 a, c

7. Laboratory assignment:
   Run through the first Synario tutorial (which you can find here). You should work through the following topics:
   • STARTING UP SYNARIO
   • INTRODUCING PROJECTS
   • ADDING FILES TO THE PROJECT
   • REMOVING FILES FROM THE PROJECT
   • INTRODUCING SCHEMATICS
   • INTRODUCING SIMULATION

8. Laboratory assignment:
   Using Synario, draw a schematic circuit for a full adder. This full adder has three inputs, A, B and CI (carry in) and two outputs, SUM and COUT (carry out). After entering the schematic, simulate it using the following test fixture (which can also be found in U:\cse370\Winter98\HW2).
   Hand in your schematic and the results of your simulation. It should be easy to see from your simulation that your circuit works.

   // CSE 370 Example:  Verilog test fixture for full adder
   // Mat Martineau 1/8/1998
   
   `timescale 1 us / 1 us
   module carrytest;  // Your module name must be different from the first
                      // eight letters of your schematic filename
   
   `include "carry.tfi" // This should be the same as your schematic
                        // filename, except with a ".tfi" extension.
   
   initial begin  // Start test
   
     // Assumes the inputs to your carry unit are A, B, and CI (carry in).
     // Change the names if you need to.
   
     A = 0;  B = 0;  CI = 0;  // Set the inputs
     #10                      // Time delay (10 microseconds)
     A = 0;  B = 0;  CI = 1;  // Change the inputs
     #10                      // Wait
     A = 0;  B = 1;  CI = 0;  // etc...
     #10
     A = 0;  B = 1;  CI = 1;
     #10
     A = 1;  B = 0;  CI = 0;
     #10
     A = 1;  B = 0;  CI = 1;
     #10
     A = 1;  B = 1;  CI = 0;
     #10
     A = 1;  B = 1;  CI = 1;
   
   end // End test
   
   
   endmodule
   

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