PPT Slide
7 – Sequential Logic Examples
© 1996 Gaetano Borriello
Digital combination lock (PLD mapping)
51
E0900
+---------\ /---------+
| \ / |
| ----- |
clk | 1 40 | Vcc
| |
rst | 2 39 | C2_4
| |
C1_1 | 3 38 | C1_4
| |
C2_1 | 4 37 | C3_3
| |
code1 | 5 36 | C3_4
| |
code2 | 6 35 | value1
| |
code3 | 7 34 | value2
| |
code4 | 8 33 | value3
| |
equal1 | 9 32 | value4
| |
equal2 | 10 31 | new
| |
mux1 | 11 30 |
| |
mux2 | 12 29 |
| |
mux3 | 13 28 |
| |
out | 14 27 |
| |
| 15 26 |
| |
| 16 25 |
| |
C3_1 | 17 24 | C2_3
| |
C1_2 | 18 23 | C1_3
| |
C2_2 | 19 22 | C3_2
| |
GND | 20 21 |
| |
| |
`---------------------------'
40 pin chip
Enough registers and input pins
Does not include code registers
requires separate chip with 12 register bits
Previous slide
Next slide
Back to first slide
View graphic version