PPT Slide
7 – Sequential Logic Examples
Outputs as part of state vector
Reuse outputs as state bits
- use outputs to help distinguish states
- why create new functions for state bits when output can serve as well in a synch-Mealy realization common in PLDs?
HG = ST'•H1'•H0'•F1•F0' + ST•H1•H0'•F1'•F0 HY = ST•H1'•H0'•F1•F0' + ST'•H1'•H0•F1•F0' FG = ST•H1'•H0•F1•F0' + ST'•H1•H0'•F1'•F0' HY = ST•H1•H0'•F1'•F0' + ST'•H1•H0'•F1'•F0
Output patterns are unique to states, we do not need ANY state bits – implement 5 functions (one for each output) instead of 7 (outputs plus 2 state bits)