PPT Slide
7 – Sequential Logic Examples
Traffic light controller (HDL description)
interface (clk, C, reset, TS, TL -> Q0, Q1, HG, HY, HR, FG, FY, FR, ST);
title 'traffic light controller'
"Inputs clk, C, rst, TS, TL pin; "Outputs (registered) Q0, Q1 pin istype 'reg,buffer'; "Outputs (combinational) HG, HY, HR, FG, FY, FR, ST pin istype 'com'; "Aliases for state register SREG = [Q0,Q1]; S0 = [0,0]; S1 = [0,1]; S2 = [1,0]; S3 = [1,1]; EQUATIONS
SREG.clk = clk; HG = (!Q0 & !Q1); HY = (!Q0 & Q1); HR = ( Q0 & !Q1) # ( Q0 & Q1); FG = ( Q0 & !Q1); FY = ( Q0 & Q1); FR = (!Q0 & !Q1) # (!Q0 & Q1);
state S0: if rst then S0 with ST = 1 else if (TL & C) then S1 with ST = 1 else S0 with ST = 0; state S1: if rst then S0 with ST = 1 else if TS then S2 with ST = 1 else S1 with ST = 0; state S2: if rst then S0 with ST = 1 else if (TL # !C) then S3 with ST = 1 else S2 with ST = 0; state S3: if rst then S0 with ST = 1 else if TS then S0 with ST = 1 else S3 with ST = 0; END
combined Moore and Mealy behavior in ABEL