PPT Slide

7 – Sequential Logic Examples

© 1996 Gaetano Borriello

Complex counter (state encoding in HDL)

18

MODULE counter

interface (clk, M, rst -> Z0..Z2);

TITLE 'binary and Gray code counter'"Inputs clk, M, rst pin;"Outputs [Z0..Z2] pin istype 'reg,buffer';"Aliases for state register and encoding SREG = [Z0..Z2]; S0 = [0,0,0]; S1 = [0,0,1]; S2 = [0,1,0]; S3 = [0,1,1]; S4 = [1,0,0]; S5 = [1,0,1]; S6 = [1,1,0]; S7 = [1,1,1];

EQUATIONS

SREG.clk = clk;

SREG.clr = rst;STATE_DIAGRAM SREG

 state S0: goto S1; state S1: if M then S3 else S2; state S2: if M then S6 else S3; state S3: if M then S2 else S4; state S4: if M then S0 else S5; state S5: if M then S4 else S6; state S6: goto S7; state S7: if M then S5 else S0;END

• ABEL-HDL description including state encoding

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