PPT Slide
7 – Sequential Logic Examples
Timing in finite state machines (cont'd)
Positive edge-triggered synchronous system
before rising edge: outputs and next state being computed
on rising edge: outputs and next state are latched into FFs
after propagation delay: outputs and next state are stable outputs may incur extra decoding delay
inputs can change after clock edge and hold time: must settle into new values while allowing enough time for new outputs and state to be computed before next clock edge