PPT Slide
4 – Combinational Logic Design Examples
Arithmetic logic unit design
Sample ALU – clever multi-level implementation
first-level gates
use S0 to complement Ai S0 = 0 causes gate X1 to pass Ai S0 = 1 causes gate X1 to pass Ai'
use S1 to block Bi S1 = 0 causes gate A1 to make Bi go forward as 0 (don't want Bi for operations with just A) S1 = 1 causes gate A1 to pass Bi
use M to block Ci M = 0 causes gate A2 to make Ci go forward as 0 (don't want Ci for logical operations) M = 1 causes gate A2 to pass Ci
other gates
for M=0 (logical operations, Ci is ignored)
Fi = S1 Bi xor (S0 xor Ai) = S1'S0' ( Ai ) + S1'S0 ( Ai' ) + S1 S0' ( Ai Bi' + Ai' Bi ) + S1 S0 ( Ai' Bi' + Ai Bi )
for M=1 (arithmetic operations)
Fi = S1 Bi xor ( ( S0 xor Ai ) xor Ci ) =
Ci+1 = Ci (S0 xor Ai) + S1 Bi ( (S0 xor Ai) xor Ci ) =
full adder with inputs S0 xor Ai, S1 Bi, and Ci (note that Bi (Ai xor Ci ) = Ai Bi + Bi Ci)