PPT Slide

4 – Combinational Logic Design Examples

© 1996 Gaetano Borriello

Overflow conditions

• Overflow when carry into sign bit position is not equal to carry-out

27

5

3

– 8

0 1 1 1  0 1 0 1 0 0 1 1 1 0 0 0

– 7

– 2

7

1 0 0 0  1 0 0 1 1 1 1 01 0 1 1 1

5

2

7

0 0 0 0  0 1 0 1 0 0 1 0 0 1 1 1

– 3

– 5

– 8

1 1 1 1  1 1 0 1 1 0 1 11 1 0 0 0

overflow

overflow

no overflow

no overflow

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