Formalize the problem

4 – Combinational Logic Design Examples

© 1996 Gaetano Borriello

• Truth table

  • show don't cares

• Choose implementation target

  • if ROM, we are done
  • don't cares imply PAL/PLAmay be attractive

• Follow implementation procedure

  • minimization using K-maps

7

A B C D C0 C1 C2 C3 C4 C5 C6

0 0 0 0 1 1 1 1 1 1 0

0 0 0 1 0 1 1 0 0 0 0

0 0 1 0 1 1 0 1 1 0 1

0 0 1 1 1 1 1 1 0 0 1

0 1 0 0 0 1 1 0 0 1 1

0 1 0 1 1 0 1 1 0 1 1

0 1 1 0 1 0 1 1 1 1 1

0 1 1 1 1 1 1 0 0 0 0

1 0 0 0 1 1 1 1 1 1 1

1 0 0 1 1 1 1 0 0 1 1

1 0 1 – – – – – – – –

1 1 – – – – – – – – –

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