PPT Slide

3 – Combinational Logic Implementation

© 1996 Gaetano Borriello

Combinational logic implementation summary

• Multi-level logic

  • conversion to NAND-NAND and NOR-NOR networks
  • transition from simple gates to more complex gate building blocks
  • reduced gate count, fan-ins, potentially faster
  • more levels, harder to design

• Time response in combinational networks

  • gate delays and timing waveforms
  • hazards/glitches (what they are and why they happen)

• Regular logic

  • multiplexers/decoders
  • ROMs
  • PLAs/PALs
  • advantages/disadvantages of each

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