PPT Slide

3 – Combinational Logic Implementation

© 1996 Gaetano Borriello

Read-only memories

• Two dimensional array of 1s and 0s

  • entry (row) is called a "word"
  • width of row = word-size
  • index is called an "address"
  • address is input
  • selected word is output

54

decoder

0 n-1

Address

2 -1

n

0

word[i] = 0011word[j] = 1010

bit lines (normally pulled to 1 through resistor – selectively connected to 0 by word line controlled switches)

j

i

internal organization

word lines (only one is active – decoder is just right for this)

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