Design an 8 bit carry lookahead adder for unsigned numbers, with carry
in and carry out. Use 2 bit carry lookahead blocks (instead of 4 bit as
in class). What is the worst case gate delay? What would the delay be if
your adder was expanded to 2**n bits? Turn in your ABEL/schematic files
and simulation waveforms (for 255 + 1, 127 + 128, and 29 + 228).
Use the adder created above to make a universal adder/subtractor. In
addition to the A and B input buses, it will have a subtract input and
a function code input. You may implement sign magnitude arithmetic by converting
inputs to 1's complement, perform 1's complement arithmetic, and then converting
outputs to sign magnitude form. Simulate the operations 4 + 10, (-4) -
(-10), (-4) - (+10), 4 + (-10) for each of the three representations. Turn
in your ABEL/schematic source files, and simulation waveforms.
F1
F0
S
function
0
-
0
2's complement add A+B
0
-
1
2's complement subtract A-B
1
0
0
1's complement add A+B
1
0
1
1's complement subtract A-B
1
1
0
sign magnitude add A+B
1
1
1
sign magnitude subtract A-B
Rationale:
To gain facility with hierarchical design.
To reinforce understanding of basic arithmetic building blocks.