CSE370 Assignment 4

Distributed: 25 April
Due: 5 May

Reading:

Chapter 4 (pp. 181-194, 202-224) and Chapter 5 (pp. 240-277) of Katz.

Exercises:

1. Katz exercise 4.16 (b,c). Use gates as necessary in (c). What subset of inputs used as selects for part (c) results in the fewest additional gates (inverted inputs are free)?
2. Katz exercise 4.17 (e). Can you choose multiplexer selects so that no complemented inputs are needed?
3. Create an ABEL module that implements the BCD to seven segment decoder described in Katz section 4.5. Use the truth table format described in the Synario tutorial. Minimize the logic using Synario. Turn in your ABEL file and the resulting minimized equations.
4. Create an ABEL module that implements the logic function unit described in section 4.6. Use the WHEN-THEN-ELSE format. Simulate your design for all input combinations. Sequence the inputs so that the four combinations of A,B are together for each function specified by C0,C1,C2. Is the output correct? Minimize the logic using Synario. By hand, implement the logic using a multiplexer with A,B as selects. Turn in your ABEL file, simulation waveforms, and the resulting minimized equations.
5. Map your ABEL design from the previous exercise onto an E0320 PLD and make sure that it fits. Turn in the chip report produced by mapping your design onto an E0320, including equations.

Rationale:

• To practice logic design using regular logic such as multiplexers.
• To learn to use hardware description language (HDL) specifications for combinational circuit design.
• To gain facility with using design tools for two-level logic minimization.
• To introduce the concept of mapping HDL specifications to programmable logic devices.