CSE370 Assignment 3

Distributed: 11 April
Due: 18 April

Reading:

Chapter 3 (pp. 110-122) and Chapter 4 (pp. 160-173) of Katz.

Exercises (see pages 103-109 and 154-159):

1. Katz exercise 2.19 (b), but express answer in product of sums form.
2. Katz exercise 2.20 (c), but express answer in sum of products form.
3. Katz exercise 2.27 (a, c). You need not compare (c) to (b) as requested in the book.
4. Katz exercise 3.2 (c).
5. Katz exercise 3.8 (b).
6. Complete the CSE370 Synario Tutorial.
7. Create a Synario project for a two input XOR gate with inputs A, B and output F. Use only NAND gates. Turn in your schematic.
8. Create a four bit XOR gate using your XOR block from above. The inputs should be A3, A2, A1, A0 and output F. Turn in your schematic.
9. Use Synario to simulate your four bit XOR for A=7, A=8, A=9, and A=13, where A = [A3,A2,A1,A0]. Turn in the waveform output of the simulator showing all output signals.

Rationale:

• To practice and gain facility with two-level minimization.
• To understand the advantages of specifying don't care conditions for combinational circuits.
• To practice combinational logic design.
• To gain some familiarity with analysis and synthesis of multi-level logic.