Retime design

• OPEN is delayed by AND gate after Q1 and Q0

  • This delay can be removed by retiming
  • Move output logic (AND gate) to eliminate delay
  • OPEN = Q1Q0 = reset'(Q1+D+Q0N)(Q0'N+Q0N'+Q1N+Q1D) = reset'(Q1Q0N'+Q1N+Q1D+Q0'ND+Q0N'D)

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