Synchronous versus asynchronous FSMs

• Synchronous FSMs

  • State changes are timed by a system clock
  • We will design only synchronous machines in CSE370

• There exist asynchronous FSMs

  • State changes are self-timed
    • Transistor speed and supply voltage set circuit speed
  • Logic blocks communicate using handshaking
    • Request and acknowledge

• Asynchronous design: A tool for the coming decade

  • Clock skew precludes synchronizing an entire high-speed chip
  • Solution: Islands of synchronous logic in an asynchronous sea

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