Sequential logic building blocks

• What you should know

  • Latches
    • R-S and D
  • Flip-flops
    • Master/slave D, edge-triggered D, edge-triggered T
  • Latch and flip-flop timing
    • Setup times, hold times, propagation delays
  • Timing diagrams
  • Flip-flop clocking
    • Synchronous versus asynchronous
    • Clock skew
  • Asynchronous inputs and metastability
  • Registers

Previous slide

Next slide

Back to first slide

View graphic version