D flip-flop timing
th 5ns
tw 25ns
tplh 25nsmax 13nstyp
tphl 40nsmax 25nstyp
tsu 20ns
D
CLK
Q
th 5ns
tsu 20ns
Signal timing must satisfy:
Setup and hold times
Minimum clock width
Propagation delays (low to high, high to low, max and typical)
IN
Q
D
Q
>
CLK
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