Clocking and timing: System considerations
Use edge-triggered flip-flops where possible
- Found in programmable logic devices
- Custom integrated circuits use level-sensitive latches
Basic rules for correct timing:
- Flip-flops are clocked synchronously (at the same time)
- For most real flip-flops: propagation delay > hold time
- No flip-flop changes state more than once per clock cycle
- Avoid mixing positive-edge triggered and negative-edge triggered flip-flops in the same circuit