Latches versus flip-flops

Type When inputs are sampled When output is valid

unclocked always prop delay from change in input latch

level-sensitive clock high, and prop delay from change in input, latch tsu/th around falling or from clock edge  edge of clock (whichever is later)

master-slave clock high, and prop delay from falling edgeflip-flop tsu/th around falling of clock edge of clock

negative clock hi-to-low transition; prop delay from falling edgeedge-triggered tsu/th around falling of clockflip-flop edge of clock

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