Sequential logic: What you should know (con’t)
Finite state machines
- Timing diagrams (synchronous FSMs)
- Moore versus Mealy versus registered Mealy
- FSM design procedure
1. Understand the problem (state diagram and state-transition table)
2. Determine the machine’s states (minimize the state diagram)
3. Encode the machine’s states (state assignment)
4. Design the next-state logic (minimize the combinational logic)
5. Implement the FSM
- FSM design guidelines
- Separate data path and control
- Encode the FSM states carefully
- One-hot encoding