Estimate the PLD fit

• Inputs

  • clk, rst, new
  • C1_1...C1_4, C2_1..C2_4, C3_1..C3_4
  • value1...value4

• Combinational outputs

  • equal

• Registered outputs

  • mux1..mux3
  • open

• Estimate PLD complexity

  • One register for each output (each state bit) ?  5 blocks
  • 3 minterms (one per bit) for equal, plus 1 (for AND gate) ?  4 blocks
  • PLD needs 19 inputs and 1 output

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