Here are some comments regarding Homework 3. The weightage for individual problems was as follows: 4.6 : 10 points (3 + 3 + 4) 4.8 : 10 points 4.11 : 10 points (5 + 5) 4.15 : 10 points (2.5 x 4) 4.18 : 20 points (7 + 7 + 8) ------------------- Total 60 points 4.6 c) For the implementation of decoder using transmission gates, be careful to avoid the hanging output problem. For details, see p 175 in the text. An advantage of Tx gates is that they have lower delays. 4.8 Implementing with a 32:1 Mux is trivial, so I was looking for 16:1 or smaller Mux. Some of you got the tricky solution with an 8:1 and a 2:1 Mux. The basic idea is to implement (C'D + BD'+ B'D + B'CE) with an 8:1 Mux, and then OR with A. OR function can be implemented with a 2:1 Mux. 4.11 For this question, I have accepted solutions which assume complemented vars are also available (as i mentioned in a previous mail) 4.15 b) Only the '1' outputs should be connected to the OR gate, the rest should not be connected. The other inputs to the OR gates should be given 0. Connecting all the 16 outputs to OR gate wont work because OR gate is always going to output 1, no matter what the input. Some of you saw this and tried to invert the '0' output terms before feeding to OR gate. That doesn't work either. This is because when the i^th output is inactive, its 0 and when you complement it, OR gate incorrectly outputs '1'. c) You had to show the word contents of each location in the ROM. The ROM need not contain all the 16 addrs, but just 1 bit word, for the output of the function. 4.18 b) Sharing of terms can be used to reduce the no. of terms from 6 to 4. The scores range from 40 thru' 60, with the mean being around 55. Feel free to come to me if you have any questions regarding grading or course material. My next office hours are on Thu 1:30 in 326 Sieg. -Nitin