Synario has several features which allow for signals to be wider that 1 bit -- to group signals into buses. The two most useful and robust are using buses in Verilog Test Fixtures and displaying buses in the Waveform Viewer
initial begin #0 I0 = 0; I1 = 0; I2 = 0; I3 = 1; #5 I0 = 0; I1 = 0; I2 = 1; I3 = 0; #5 I0 = 0; I1 = 1; I2 = 0; I3 = 0; #5 I0 = 1; I1 = 0; I2 = 0; I3 = 0; endKeeping track of all the
I0
's, I1
's,
I2
's, and I3
's is a chore, and the
.tf
ends up being dozens of lines long for only a few
simple test cases.Instead, we can use Verilog's signal concatenation syntax to build buses out of the several individual variables. The syntax is very simple:
{
signal1 ,
signal2
,
signal3 ,
...
}
So for example, we could make the first assignment above with:
{I3,I2,I1,I0} = 4'b1000;
The 4'b1000
is notation for a binary value 4 bits long,
whose value is 1000.
Thus, the whole intial
block of the file could be
rewritten as:
initial begin #0 {I3,I2,I1,I0} = 4'b1000; #5 {I3,I2,I1,I0} = 4'b0100; #5 {I3,I2,I1,I0} = 4'b0010; #5 {I3,I2,I1,I0} = 4'b0001; end
It is usually best to have the high-order bits first, so click Reverse to order the pines out3, out2, out1, out0.
Click on the $Bus1 to change the name of your bus. I'll use 'out'. Click on Save Bus, and the bus will be created.
Finally, click on show to show the bus in the waveform viewer.
As a final step, you can change the radix of the bus from hexadecimal
(the default) to octal, binary, or decimal. From the Options menu,
select Bus Radix, and then click on the desired radix. The resulting
out
bus in the waveform viewer now looks like: