# Buses in Synario

The whole of computer hardware isn't defined or built out of individual 1-bit signals. There is always a need for grouping several signals together in buses. Examples are the 4 bits of input or output of the shift register in homework 7, or the 8 bit result from the ALU in homework 6.

Synario has several features which allow for signals to be wider that 1 bit -- to group signals into buses. The two most useful and robust are using buses in Verilog Test Fixtures and displaying buses in the Waveform Viewer

## Buses in Verilog Test Fixtures

It isn't any fun to write a test fixture file that looks like:
```  initial begin

#0	I0 = 0;
I1 = 0;
I2 = 0;
I3 = 1;

#5	I0 = 0;
I1 = 0;
I2 = 1;
I3 = 0;

#5	I0 = 0;
I1 = 1;
I2 = 0;
I3 = 0;

#5	I0 = 1;
I1 = 0;
I2 = 0;
I3 = 0;
end
```
Keeping track of all the `I0`'s, `I1`'s, `I2`'s, and `I3`'s is a chore, and the `.tf` ends up being dozens of lines long for only a few simple test cases.

Instead, we can use Verilog's signal concatenation syntax to build buses out of the several individual variables. The syntax is very simple:

`{` signal1 `,` signal2 `,` signal3 `,` ... `}`

So for example, we could make the first assignment above with:

`{I3,I2,I1,I0} = 4'b1000;`

The `4'b1000` is notation for a binary value 4 bits long, whose value is 1000.

Thus, the whole `intial` block of the file could be rewritten as:

```  initial begin
#0	{I3,I2,I1,I0} = 4'b1000;
#5	{I3,I2,I1,I0} = 4'b0100;
#5	{I3,I2,I1,I0} = 4'b0010;
#5	{I3,I2,I1,I0} = 4'b0001;
end
```

## Buses in the Waveform Viewer

To create a bus in the waveform viewer, begin by monitoring all the pins that will eventually be in your bus. In the waveform viewer, select some signal that will not be in your bus. Now, click and drag across all the signals that you'd like included in your bus. (If you click and drag on the currently selected signal, you will move that signal in the waveform viewer, instead of selecting multiple signals). From the Edit menu, select Add To Bus... On the right hand panel, you should see your signals, as shown below:

It is usually best to have the high-order bits first, so click Reverse to order the pines out3, out2, out1, out0.

Click on the \$Bus1 to change the name of your bus. I'll use 'out'. Click on Save Bus, and the bus will be created.

Finally, click on show to show the bus in the waveform viewer.

As a final step, you can change the radix of the bus from hexadecimal (the default) to octal, binary, or decimal. From the Options menu, select Bus Radix, and then click on the desired radix. The resulting `out` bus in the waveform viewer now looks like: