CSE370 Assignment 9

Distributed: 2 December
Due: 11 December

Reading:

Chapter 11 (pp. 556-590) and, optionally, Chapter 12 (pp. 601-639) of the Katz text.

Project statement:

You are to complete the design of a simple processor based on an accumulator architecture. The processor has 8-bit instructions and 8-bit data stored in two separate memories, a ROM and RAM, respectively. There are 32 words in each memory, therefore, addresses for both instructions and data are only 5 bits. The data memory has a special feature, namely, address 31 is read- only and the data consists of the value placed by the user on 8 input wires. This permits user inputs from your simulator test fixtures without having to recompile the data memory module.

The processor executes the following instruction set:

Mnemonic    Format        Description
----------------------------------------------------------------
HALT        000  XXX00    halt execution of processor
CLR         000  XXX01    set accumulator to 0
INC         000  XXX10    increment accumulator by 1
DEC         000  XXX11    decrement accumulator by 1
STORE       001  addr     store value in accumulator into data memory at address addr
JMPZ        010  addr     load addr into PC if accumulator is zero
JMP         011  addr     load addr into PC unconditionally
ADD         100  addr     add value in data memory at address addr to accumulator
SUB         101  addr     subtract value in data memory at address addr from accumulator
LOAD        110  addr     load value in data memory at address addr into accumulator

The instruction set is divided into two categories: instructions that reference the data memory, and those which do not. The distinction is made in the 3 most significant bits of the instruction (000 signifying an instruction that does not utilize the data memory). Instructions which reference memory use the upper 3 bits as the opcode.

Of course, I wouldn't expect you to design an entire processor from scratch in the last week of the quarter. After all, you have already designed and ALU and its registers and a fairly complex state machine in the last assignment. You will find the complete project file for the processor as well as all the specification files for the data path and memories in U:\cse370\hw9\*.syn. The file U:\cse370\hw9\proc.syn is the high-level specification for the design. All its submodules are complete and are in Synario projects of their own.

The major components of the system are described below. Please refer to the ABEL files and schematic attached to this assignment for further details.

1. AC consists of the ALU and the accumulator register. It is broken into two nibbles of 4 bits each for PLD fitting purposes. The ALU is very similar to the ALU you completed for assignments 6 and 8 except that it does not perform the XOR operation (operation code 3). Each nibble is composed of 4 full adders. Multiplexers on each of the inputs of the full adder (a, b, and cin) provide the ability to implement the different functions. Each clock cycle the accumulator register (areg) is loaded with the sum output of the full adders. Clearing the AC is implemented by sending 0s into all the inputs of the full adders. Incrementing is implemented by setting the B input to 0 and expecting a carry-in of 1. Decrementing is implemented by expecting the B input to be all 1s. Similarly, subtraction is implemented by expecting the B input to be the 1s complement of the number to be substracted and the carry-in is expected to be 1 to complete generating the 2s complement. Adding this burden to whatever module provides the B input, permits a smaller design for the ALU/AC nibble that lets it fit into two E0600 PLDs. This module together with the BREG module forms the data path of the processor.
2. The BREG module is the other registered input of the ALU. The B register can take its input from itself (to hold its value), can be set to all 1s (needed for decrementing in the ALU), can take its input from the output of the data memory (to bring a memory value into the data path), or can take its input to be the complement of itself (needed for implementing subtraction in the ALU). This module together with the AC module forms the data path of the processor.
3. The PC module is quite similar in function to the AC module. It has a much simpler ALU that is capable of loading the PC with the value of the other input (the IR or instruction register) to implement a jump instruction, incrementing the PC by 1 to advance to the next instruction, or holding its current value. This simpler ALU permits the design of this module to fit into a single E0600 PLD rather than two. This module together with the IR module forms the instruction data path of the processor.
4. The IR module is quite similar to the BREG module. It has a simpler function in that the value of the register can be loaded from the output of the instruction memory or be kept the same. This module together with the PC module forms the instruction data path of the processor.
5. The instruction memory is a simple ROM. The 5 address bits cause the output to be the value of the indexed word in memory. The ROM is already loaded with a program that adds the numbers from 1 to N. N is input using the special input method of address 31 in the data memory. Pay special attention to this file as it shows how the instructions are assembled into the 1s and 0s of our machine’s code.
6. The data memory is a simple RAM. It has one special feature in that address 31 is a read-only word whose value can be set by the user outside of the module. This permits a way of entering a single data value without having to change the contents of any of the ABEL files describing the memories.
7. Finally, the CONTROL module is the one that you must complete. It generates all the control signals to all the other modules and will consist of a finite-state machine that will cycle through a fetch, decode, execute cycle.

The data path of the processor has already been mapped to E0600 PLDs. There are two for the AC module and one each for the BREG, PC, and IR modules for a total of five PLDs. Many of the decisions made in the design of the AC module were based on fitting a four-bit ALU into a single PLD. Thus, some functions were left to the BREG module to implement.

Exercises:

1. Read this assignment carefully and review the ABEL files and schematic attached. Have questions prepared for the class lectures on 4 December and 6 December. Copy all the files in U:\cse370\hw9\*.* to your home directory.
2. Complete the design of the processor by generating a state diagram for the control module to be implemented as a synchronous Mealy machine. Turn in the state diagram and your register-transfers for each cycle of each instruction as well as for the instruction fetch cycle.
3. Fit your control module design onto the cheapest set of PLDs (you may use E0320s or E0600s, assume that the cost of an E0320 is 75% that of and E0600). Turn in ABEL files for each of your PLDs.
4. Have your processor run the program given in the instruction memory ABEL file. Turn in waveforms that show the contents of each of the registers (state register in the CONTROL module, areg, breg, pc, and ir) as well as any other important signals (e.g., zero) for the entire operation of the program when N=3. This may be quite a long waveform. Display all multibit signals as buses. Examples of this are in all the .tf files given to you.

Rationale:

• To develop an understanding of the operation of a simple processor.
• To gain facility with the design of finite-state controllers.
• To appreciate the tradeoffs made when mapping a design to a specific implementation technology.