Design the main data-path component of the CSE370 processor you will
complete in the last assignment. The data-path consists of two parts, one
for data and one for instruction processing. We will design our processor
so that the same component can be used for both parts. This component will
consist of the ALU you designed in Assignment 6 augmented with 2 8-bit
registers at its inputs. One of the registers will serve as the
accumulator register and will have its inputs directly connected to the
outputs of the ALU. Each register should also have a separate control
signal indicating when it should be loaded with a new value and when it
should just hold its current value. Thus, the data path element should
have 6 control signals (LoadA, LoadB, ALUop1, ALUop2, ALUop3, EnaA), 3
status outputs (equal to zero, less than zero, and overflow), an 8-bit data
inputs (to register B), and an 8-bit tri-stateable output (from register
A). The data path element should look like this:
To be able to tri-state an output, you'll need to use the ABEL .OE
suffix. Writing Areg.OE = EnaA; in your EQUATIONS is all
you need to do if Areg is aliased to the 8 flip-flops in your A
register (e.g., Areg = [A7..A0];).
Turn in your ABEL and/or schematic files along with simulation waveforms
that show in consecutive cycles: the value 7 being loaded into the B register,
the value in B transferred to the register A while a new value of 1 is loaded
into B, the ALU performing the "A+B" operation and placing the result in A,
clear the value of A to 0.