## CSE370 Assignment 7

### Distributed: 13 November Due: 20 November

Chapter 7 (pp. 337-345) and Chapter 8 (pp. 383-395 and 400-412) of the Katz text.

#### Exercises:

1. Load the project in U:\cse370\hw7\mystery.syn which describes two sequential logic elements. Via simulation only (do not look at the contents of the .abl file), determine the type of the sequential logic elements (e.g., negative edge-triggered flip-flop, positive level-sensitive latch, etc.). You will need to write your a test fixture that uses the d12 and clk inputs and observe the q1 and q2 outputs. The clock period has been setup to be 10 time units. To specify the clock period you can use a parallel initial construct that does nothing more than toggle the clock. The Verilog simulator will run the two initial blocks in parallel. In this manner, you can focus on just changing the input in its own initial block.
````timescale 1 ns / 1 ns
module mystery_module;

`include "mystery.tfi"

initial begin

clk = 0;

forever begin
#5 clk = 1;
#5 clk = 0;
end

end

initial begin

#1 d12=0;
#10 d12=1;
. . .

end

endmodule
```
Turn in simulation waveforms and an explanation of how the waveforms let you arrive at your conclusions.
2. In ABEL, one can specify a flip-flop by declaring a signal type to be 'reg'. Furthermore, this can be modified by 'buffer' or 'invert' to tell ABEL that the signal should be not inverted or inverted at the pin, respectively. This creates a flip-flop that has several associated signals. These are specified using the following extensions to the signal name: .CLK, .FB, .CLR, .SET, .ACLR, and .ASET. These are the clock input, the value of the flip-flop output (that is fed back into the combinational logic), synchronous clear and set, and asynchronous clear and set. Assignments to the 'reg'istered signal are done using the := assignment operator rather than =.
What is the function specified by the following ABEL code? Provide a couple of English sentences describing what the circuit does (e.g., looks for the pattern 101 and generates a high output whenever it sees it on the input signal.
```MODULE simple

interface (x, clr, clk -> z);

TITLE 'simple sequential circuit'

x, clr, clk   pin;
z             pin istype 'reg, buffer';

EQUATIONS

z.clk  = clk;
z.clr  = clr;
z     := z.fb # x;

END
```
In addition, you should map your .abl file to a E0320 PLD. You'll note that this PLD (see the schematic for the PLD handed out with Assignment 5) does not have flip-flops with a clear/reset input. Thus, if you look at the "Chip Report" you'll see that the ABEL compiler will change the equation for the input to the flip-flop to include clr as an input signal as follows:
``` z.D = ( !clr & z.Q  # !clr & x );
z.C = ( clk );
```
You will also note that the flip-flop being used is clearly a D FF and "z :=" has been
replaced by "z.D =" and "z.fb" has been replaced by "z.Q".

This is possible one the compiler knows the type of flip-flop being used. In the original specification, things were more generic so that the compiler could map to different FF types (e.g., RS, D, JK, etc.).

Turn in simulation waveforms and an explanation of how the waveforms let you arrive at your conclusions.

3. Design a 4-bit universal shift register. It should implement the following functions specified by its S2, S1, and S0 control inputs: (000) hold, (001) circular right shift, (010) circular shift left, (011) logic shift right, (100) logic shift left, (101) arithmetic shift right, (110) arithmetic shift left, (111) parallel load. See exercise 7.2 in the Katz text for a definition of these shift operations (pp. 374). You can construct your design hierarchically within ABEL or using a combination of ABEL and schematics. You can reference a submodule in ABEL by first declaring its interface and then instantiating a copy as follows (these statements are placed in the declaration section before the equations):
``` counter interface (clk, rst -> q7..q0);
cntr1 functional_block counter;
```
You can then refer to the inputs and outputs of the cntr1 instance of the counter module using the "." extension notation (e.g., cntr1.rst (the reset input of the counter module instance), cntr1.[q7..q0] (the 8-bit output of the counter module instance)).

Your shift register sub-module should consist of a cell with a single flip-flop and three inputs (DI, SR, and SL). There should also be two control inputs: S0 and S1. When S0 and S1 are (11), DI should be loaded into the flip-flop, for (01) SL should be loaded in, for (10) SR should be loaded in, and for (00) the flip-flop should hold its current state.

Turn in you ABEL and/or schematic files and simulation waveforms that show your shift register loading in the pattern 1011 and then performing an circular shift right, followed by an arithmetic shift right, followed by a hold, followed by a logical shift left, followed by another logical shift left.

4. Create a counter that counts in Gray code (000, 001, 011, 010, 110, 111, 101, 100, 000, ... ). It should have a reset signal that sets it to 110 and an enable input that stops the counter when low. Map your design to an E0320 PLD.

Turn in your ABEL file and waveforms for a simulation that begins by resetting the counter and the counts for 9 clock cycles. Include a state diagram for the counter. Also turn in a map of the E0320 PLD showing how the ABEL compiler maps the design to the PLD.

#### Rationale:

• To develop an understanding of basic sequential logic elements.
• To learn to use hierarchy in a hardware description language.
• To learn to use a hardware description language for the specification of sequential logic.

Comments to: cse370-webmaster@cs.washington.edu (Last Update: 12/01/96 )