Due: 13 November

Chapter 6 (pp.282-313) and Chapter 7 (pp. 329-337) of the Katz text.

- Create a new symbol for a 4-bit adder. This time specify
it directly in ABEL. Make sure to include a carry-in and a carry-out.
Take advantage of ABEL's arithmetic specification capabilities, that
is, use the '+' arithmetic operator in your specification.

*Turn in ABEL file and simulation waveforms (for 7 + 1, 5 + 10, and 6 + 10).* - Design an 8-bit carry-select adder for unsigned numbers.
It should be designed hierarchically at the schematic diagram level
and include 3 copies of the 4-bit adder block you designed in the
previous exercise. Compare the delay of the adder for the worst case
11111111 + 00000001 to the delay of a ripple-carry adder.

*Turn in schematic file and simulation waveforms (for -1 + 1 (the worst case delay), 127 + (-128), and -37 + 38).* - Design an 8-bit ALU for the processor you will be completing
by the end of the quarter. The numbers will be represented in 2s
complement form. You should design this ALU using ABEL to
specify each of two 4-bit slices (a low-order nibble and a high-order
nibble) and then using a schematic to put two copies together and
add any extra logic needed. You can use a simple ripple-carry adder
(so that you can use ABEL's arithmetic). Also, think of ways of
organizing your ALU so that the two ALU nibbles use the same symbol
and hence, the same ABEL file.
The ALU has 3 control signals that specify 1 of 8 functions. The data input signals should be labelled a[7:0] and b[7:0] (with a[7] and b[7] being the high-order bits), the data output signals should be labelled c[7:0], the control input signals should be labelled s[2:0], there are four other outputs: carry-out, equal-to-zero, overflow, and less-than-zero. These last three outputs are simple combinational functions.

**Control Function Comment [s2,s1,s0] --------------------------------------------------------- 000 C = 0 zero 001 C = A pass A 010 C = B pass B 011 C = A xor B bit-wise XOR of A and B 100 C = A + 1 increment A 101 C = A - 1 decrement A 110 C = A + B add A and B 111 C = A - B subtract B from A**

*Turn in schematic file and simulation waveforms for the following cases:*Operation A B ---------------------------------------------- 000 1 2 001 -128 65 010 5 10 011 15 30 100 79 65 101 0 1 110 -1 1 111 7 8

- Katz exercise 6.11(a, b, c, d) (pg. 324).
- Katz exercise 6.12(a, b, c, d) (pg. 324).

- To learn the use of higher-level construct, such as arithmetic operators, in HDL specifications.
- To reinforce speed/area tradeoffs in combinational logic design.
- To gain facility with hierarchical design and the tradeoff inherent in creating multi-purpose components.
- To reinforce understanding of the basic building blocks of sequential circuits.

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