CSE370 Assignment 5

Distributed: 28 October
Due: 4 November

Reading:

Chapter 5 (pp. 240-277) of the Katz text.
Tutorial 1: An Introduction to Synario (supplied by DataI/O Corporation).
Tutorial 2: Top Down Design Using ABEL-HDL and Schematics (supplied by DataI/O Corporation).

Exercises:

1. Complete the CSE370 Synario/ABEL Tutorial attached to this assignment.
   There is nothing to turn in for this exercise.
2. Minimize the equations of problems 2.19c and 2.19d (page 106 of the Katz text) using ABEL.
   Turn in your specification using truth-tables and the resulting equations (.eq1 file).
3. Create an ABEL module that implements an 8:1 multiplexer with data inputs (I0 through I7) and control inputs (A, B, C) and output (Z). Simulate this for the case where the data inputs are (1, 1, 1, 1, 0, 0, 0, 0, respectively) and you vary the control inputs from (0, 0, 0) to (0, 0, 1) to (1, 0, 1) to (1, 1, 1).
   Turn in your ABEL file and simulation waveforms.
4. Create a schematic that uses the multiplexer module you created for the previous exercise to implement a full-adder as in assignment 4.
   Turn in your schematic (showing connections to VCC and GND) and your simulator waveforms for all input combinations of the control inputs.
5. Create an ABEL module that implements the circuit required by problem 4.21 (page 236 of the Katz text). Map it onto an E0320 PLD and make sure that it fits.
   Turn in your ABEL file; simulator waveforms for the cases where the inputs (Input0, Input1, Input2, Input3) are (0, 0, 0, 1), (0, 0, 1, 0), (0, 1, 0, 0), (1, 0, 0, 0), (1, 0, 1, 0) and (0, 1, 0, 1); the chip report produced by mapping your design onto an E0320 including equations.

Rationale:

• To learn to use hardware description language (HDL) specifications for combinational circuit design.
• To gain facility with using design tools for two-level logic minimization.
• To practice logic design using regular logic such as multiplexers.
• To introduce the concept of mapping HDL specification to programmable logic devices.