module example (input x, input y, output [6:0] outx, output [6:0] outy); //A register is being declared here, this is because only //registers may be changed inside an always block. You cannot //use assign statements inside an always block. This means //out_r = 3; will work, but out=3; will not. reg [6:0] outx_r; reg [6:0] outy_r; //Because only registers can be changed inside an always block //we need to set the ouput to be equal to the register that we //are changing. Since Verilog runs in parallel this assignment //is always happening. Pysically you can think of connecting a wire //from the register directly to the output. assign outx = outx_r; assign outy = outy_r; //This is an always block. You read it as follows, "Always at 'x' begin" //This means that whenever 'in' changes values the code inside the always //block will be executed. always @(x) begin //This is a case statement. It is like a normal case statement, based //on the value of the case the code following it will be executed. case(x) //These are the case statements, since x only has 1 bit can only be //equal to 0 or 1. So just like the ternary that we demonstrated earlier //if x is equal to 1, we assign the value 48 to it, otherwise we assign the //value 0. 0: outx_r = 7'b0000000; 1: outx_r = 7'b0110000; //The default case is very important, in the case where x doesn't equal 0 or 1, //it will default to the default case, in this case, all x's which means no //definite value. default: outx_r = 7'bxxxxxxx; //All case statements need to be ended with an endcase statement. endcase end always @(y) begin //You can also do if statements. if (y == 0) outy_r = 7'b0000000; else outy_r = 7'b0110000; end endmodule