CSE370 Assignment 4

Distributed: 29 January 2010
Due: 3 February 2010


  1. Katz/Borriello, Contemporary Logic Design 2e, Chapter 5 (pp. 221-253)
  2. Katz/Borriello, Contemporary Logic Design 2e, Chapter 4, Section 4.2 and 4.3 (pp. 184-205)


1.      Write a Verilog module that computes DAY_OF_YEAR[8:0] given MONTH[3:0], DAY[4:0], and LEAP_YEAR flag.Use a CASE statement in Verilog to implement a lookup-table for the month offset and then perform an appropriate addition ( use this template Ė cal.v ).In addition, you should have and ERROR flag output if the MONTH is 0, 13, 14, or 15 or the DAY and LEAP_YEAR inputs donít make sense.Use the test fixture ( cal_tf.v ) to test your circuit.Make sure to read the Verilog to see how it works and the conditions it is testing.

2.      CLD-II, Chapter 5, problem 5.9

3.      CLD-II, Chapter 5, problem 5.10


  • To practice describing logic block with Verilog.
  • To measure circuit performance for complex logic such as adders.

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