Active-HDL - Tips, Hints, and Reference
(To be updated soon...)
Active-HDL is an industrial-strength design tool. Like any tool, used
in the right way, it is very powerful and productive; but there are certain and
quirks and idiosyncrasies which, if ignored, will lead to hours - yea days - of
frustration. This page gives guidelines and tips for using the tools so
that you don't run into problems. They are listed in section in
decreasing order of importance.
If you know something that should be included here, please mail it to us and we will add
it.
General Advice:
- Keep it simple and don't stray from straightforward,
proven ways of doing things. Don't expect the tools to do things the
way you think they should be done. Don't fight the tools, go with
the flow. The tools always win.
- Clean out the design cache periodically via [Design->Clear
Implementation Data] and right-click the Library [Delete Simulation
Data] This is analogous the "make clean" and will
force a complete recompile.
- If mysterious things happen that don't make sense, try
resetting things in this order:
1) Quit and restart the tools
2) Reboot the PC
3) Switch to another machine.
- Save often and backup often. The way to do this
is to make an archive [Design->Archive Design...] that you can
restore [Design->Restore Design...] if necessary. Use this
to package up designs that you need to send via email.
Schematic Editor
(Bugs):
- If you change the name of a schematic, it will not
change the name of the symbol associated with it. This also happens
if you use Save As to create a new schematic based on the current
one. You'll find out after you've made the changes and compile that
the symbol is the same name as the old component.
- To make a copy of a schematic, Add New File and then
use select-all, cut and paste to copy the circuit from the other
schematic.
Schematic Editor
(Tips):
- Always run [Diagram->Check Diagram] on your
schematics. This will find many, many errors and save you hours of
frustration.
- When you "Add an existing file", make sure
you have the "Make local copy" check box filled in.
Otherwise you will create a reference to the other file, which you
may not be able to change, and won't be included when you make an archive,
which means that the archive file is pretty useless.
- If a schematic (.bde) file name italicized and won't
compile, it probably does not have a target language. Close the file
first (important), then do [Design->Change Target HDL] and
choose Verilog. Ignore the warning. It may also indicate that
the file is not part of the compilation: Right-click on it and [Include
in Compilation]. If the
schematic editor insists on creating block diagrams with the name
italicized, use the Wizard instead to create a file.
- Each schematic has an associated symbol that you use to
make hierarchical schematics. However, changes to the schematic or
to the symbol are not reflected automatically in the other. Here's
what you have to do: Right-click on your symbol, and select
"Compare symbol with contents...". This will tell you if
there has been a change and it will ask you whether you want to change the
schematic or the symbol. Usually you want to change the symbol because
of a change you made to the schematic. Presto, things are fixed.
- When writing Verilog modules, make sure your file name
and your module name match. The symbol is going to be called by the module
name, not the file name, and this will keep you from getting confused.
- CTL-drag is a very efficient way to copy parts of a
schematic when there is lots of structure.
- SHIFT-drag allows you to move pieces of a schematic,
breaking wires, instead of extending them.
- When you name a bus, you can list signals which are
concatenated to make the bus. E.g. A[7:0], B[7:0] makes a 16 bit bus
by concatenating the two 8-bit busses A and B. You can include simple
names like GND. Sign extending is easy too:
A[3],A[3],A[3],A[3],A[3:0] to sign extend a 4 bit value to 8 bits.
- It is possible for two wires to be laid out as two 'L's
(one upside down, one right side up) corner to cornet such that it looks
*identical* to the extremely common pattern of two straight wires
crossing.
- If you want a bigger page, choose Tabloid in the Page
Setup menu. This will give you an 11x17 page. Landscape is
typically the best. You can still print as a single page by scaling
when you print, or by using ps327, which will print 11x17 pages.
- You can change the symbol for a component by
right-clicking and using the "Edit symbol in separate window"
option. I use this to move pins around to make the symbol look like
I want. Note you can move signals to the opposite side of the
symbol, i.e. inputs to the right and outputs to the left. You can
also resize the symbol, but I'd be careful about trying to do much more.
- To make a library a standard library that is attached
to all designs, add a line for the library in the \Vlib\library.cfg file
(found in the Aldec install folder). Just follow the format in that
file.
Simulator
(Bugs):
- Active-HDL has a bug which causes simulation to
sometime fail for nested arrays of symbols. That is, the simulator
may give you the wrong answer if you use an array of a components that
itself has an array of components. Aldec claims that running the
following command from the console window will fix the problem:
alog +accb +accr *.v
- If you get a "duplicate identifier"
message, it's probably because you've got several modules that define the
same symbol. (See the previous bug/tip.) You can fix this
temporarily by right-click [Remove from compilation] on the file you are
not using.
Simulator
(Tips):
- Sometimes the probes disappear from the components in a
simulation. If the Clear Implementation Data/Delete Simulation Data
trick doesn't work, you can right-click the component and [Add Probes on
all Pins]
- When you are running a simulation, make sure you have
only one waveform window open to avoid confusing yourself and the
simulator.
- Stimulators only work from the waveform window.
To watch the signals in the block diagram while using stimulators, detach
the waveform window and position it so that both the waveform and block
diagram windows are visible. Run the simulation from the waveform
window using F5 and the stimulators while watching the signals in the
block diagram window.
ebeling@cs.washington.edu