## CSE 370 Assignment #5

### Due: Friday, February 13, 2009.

Distributed: Wednesday, February 4, 2009.

1. Katz/Borriello, Contemporary Logic Design 2e, Section 4.6 (pages 164-205)

2. Katz/Borriello, Contemporary Logic Design 2e, Chapter 6 (pages 259-298)

### Exercises:

1. CLD2e pages 150-151, Chapter 3, Exercise 3.18 parts c,d.

1. Design and test a 1-bit CLA building block that takes 3 inputs, A, B and Cin and gives three outputs: Sum, P, and G. Sum is the usual full adder sum bit. P and G are the propagate and generate functions. They are defined as: G = AB, P = A XOR B. You may do this either with Verilog or a schematic. However you need a schematic for submission. Name this block add1.

2. Using the 1-bit block you just created, design and test a block which performs the above operation on 4-bit buses. Hence it has three input busses, A[3:0], B[3:0] and Cin[3:0] and generates three outputs (busses), Sum[3:0], P[3:0] and G[3:0]. (This 4-bit block is just four independent copies of the 1-bit block you created.) You must use a schematic for this. Name it add4.

3. Design and test a 4-bit carry look-ahead component that has three inputs, P[3:0], G[3:0] and Cin, and generates three outputs, Cout[3:0], BlockP, and BlockG. BlockP and BlockG are the block-propagate and block-generate functions. Note that there is only a single carry_in bit, but your block generates 4 carry bits at the output. You must predict higher order carries (Cout[1], Cout[2] and Cout[3]) based on Cin, P and G inputs. Your lecture notes for the adder might be a good way to recall how to do this. Use a schematic for this. Name it cla4.

4. Using the building blocks of part b (add4) and part c(cla4), design and test a 16-bit carry look-ahead adder. You must use a schematic for this. Name this cla16.

5. What is the size (# of gates) and delay (just the total # gates on the longest path) of your 16-bit carry look-ahead adder?

6. Could you use cla16's and cla4's to make a 64-bit adder? If you made a 64-bit carry look-ahead adder using these components, what would be the size and delay of that circuit?
Turn in screenshots of your schematic for parts a,b c,d and the answers to part e,f.

3. CLD2e page 300, Chapter 6, Exercise 6.1.

4. CLD2e page 301, Chapter 6, Exercise 6.10. Use this template.

### Rationale:

• To practice how to eliminate simple timing hazards.