CSE 370 Assignment #4

Due: Wednesday, February 4, 2009.

Distributed: Wednesday, January 28, 2009.

Reading Assignment:

  1. Katz/Borriello, Contemporary Logic Design 2e, Sections 4.2-4.3 (pages 164-205)

Exercises:

Please write legibly & show your work for full points.

  1. CLD2e page 214, Chapter 4, Exercise 4.7 parts a and b.

  2. CLD2e page 216, Chapter 4, Exercise 4.14 parts a and b. You may use inverted inputs.

  3. For the following problems, you may print the ROM, PLA and PAL worksheets or the worksheet which has all three on one page. Implement the following three functions using a ROM, PLA and PAL. For the PLA, try to minimize the number of AND gates you use.

    1. f1(a,b,c,d) = Σ m(8, 4, 12, 14, 13) + d(10, 6)

    2. f2(a,b,c,d) = Σ m(10, 12, 14) + d(6)

    3. f3(a,b,c,d) = Σ m(10, 4, 11, 13, 15) + d(9, 7)

Rationale: