## CSE 370 Assignment #3

### Due: Wednesday, January 28, 2009.

Distributed: Wednesday, January 21, 2009.

### Reading Assignment:

- Katz/Borriello, Contemporary Logic Design 2e, Sections 3.1 and 3.2.3 (pages 93-103,111-114)
- Katz/Borriello, Contemporary Logic Design 2e, Sections 4.2 (pages 164-196)

### Exercises:

Please write legibly & show your work for full points.
- CLD2e page 149, Chapter 3, Exercise 3.17. You can assume
that all literals are available.
- Minimize the following functions using K-maps and draw the logic gate
diagrams:
- F(w,x,y,z)=Π M(1,4,5,7,13) Π D(9,14,15).

Optimize this as a sum-of-products, and then use only NAND gates (and literals) in your final diagram.
- F(w,x,y,z)=Σ m(1,3,5,8,9,12)+Σ d(6,10,14).

Optimize this as a
product-of-sums and then use only NOR gates (and literals) in your final diagram.

- In this question you'll design circuits that divide two 2-bit binary
numbers A = (A1 A0) and B=(B1 B0) and
computes the 2-bit quotient Q=(Q1 Q0) of A divided by B and the remainder
R=(R1 R0) of A divided by B. In the case that B is 0 the answer is undefined
so the values on such inputs can be taken as don't cares.
- Draw truth tables for Q1,Q0,R1,R0.
- Use K-maps to minimize these in SOP form.
- Use K-maps to minimize these in POS form.

### Rationale:

- Practice circuit design and optimization with K-maps