SCHM0102 HEADER { FREEID 1082 VARIABLES { #BLOCKTABLE_FILE="#table.bde" #BLOCKTABLE_INCLUDED="1" #LANGUAGE="VERILOG" #MODULE="ShiftRegisters" AUTHOR="cse" COMPANY="uw" CREATIONDATE="10/28/2005" TITLE="No Title" } SYMBOL "lib370" "c74374" "c74374" { HEADER { VARIABLES { #DESCRIPTION="" #LANGUAGE="VERILOG" #MODIFIED="1113266907" } } PAGE "" { PAGEHEADER { RECT (0,-20,160,460) FREEID 70 } BODY { RECT 1, -1, 0 { VARIABLES { #OUTLINE_FILLING="1" } AREA (20,0,140,440) FILL (0,(255,221,221),0) } TEXT 3, 0, 0 { TEXT "$#NAME" RECT (99,389,128,413) ALIGN 6 MARGINS (1,1) PARENT 2 ORIENTATION 2 } TEXT 5, 0, 0 { TEXT "$#NAME" RECT (25,70,53,94) ALIGN 4 MARGINS (1,1) PARENT 4 ORIENTATION 2 } TEXT 7, 0, 0 { TEXT "$#NAME" RECT (25,110,52,134) ALIGN 4 MARGINS (1,1) PARENT 6 } TEXT 9, 0, 0 { TEXT "$#NAME" RECT (25,190,53,214) ALIGN 4 MARGINS (1,1) PARENT 8 ORIENTATION 2 } TEXT 11, 0, 0 { TEXT "$#NAME" RECT (25,150,52,174) ALIGN 4 MARGINS (1,1) PARENT 10 } TEXT 13, 0, 0 { TEXT "$#NAME" RECT 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TEXT 64, 0, 0 { TEXT "15" RECT (140,220,160,241) MARGINS (1,1) COLOR (0,0,0) FONT (7,0,0,400,0,0,0,"Arial") } TEXT 65, 0, 0 { TEXT "16" RECT (140,180,160,201) MARGINS (1,1) COLOR (0,0,0) FONT (7,0,0,400,0,0,0,"Arial") } TEXT 66, 0, 0 { TEXT "17" RECT (140,140,160,161) MARGINS (1,1) COLOR (0,0,0) FONT (7,0,0,400,0,0,0,"Arial") } TEXT 67, 0, 0 { TEXT "18" RECT (140,100,160,121) MARGINS (1,1) COLOR (0,0,0) FONT (7,0,0,400,0,0,0,"Arial") } TEXT 68, 0, 0 { TEXT "19" RECT (140,60,160,81) MARGINS (1,1) COLOR (0,0,0) FONT (7,0,0,400,0,0,0,"Arial") } TEXT 69, 0, 0 { TEXT "20" RECT (140,20,160,41) MARGINS (1,1) COLOR (0,0,0) FONT (7,0,0,400,0,0,0,"Arial") } PIN 2, 0, 0 { COORD (160,400) VARIABLES { #DIRECTION="IN" #LABEL="CLK" #LENGTH="20" #NAME="CP" #NUMBER="0" #SIDE="right" #VERILOG_DELAY="" } LINE 1, 0, 0 { OUTLINE 0,1, (0,0,128) POINTS ( (0,0), (-20,0) ) } LINE 2, 0, 0 { OUTLINE 0,1, (0,0,128) POINTS ( (-20,0), (-20,-10), (-30,0), (-20,10), (-20,0) ) } } PIN 4, 0, 0 { COORD (0,80) VARIABLES { #DIRECTION="OUT" #LENGTH="20" #NAME="Q0" #NUMBER="0" #SIDE="left" } LINE 2, 0, 0 { POINTS ( (20,0), (0,0) ) } } PIN 6, 0, 0 { COORD (0,120) VARIABLES { #DIRECTION="IN" #LENGTH="20" #NAME="D0" #NUMBER="0" #SIDE="left" } LINE 2, 0, 0 { POINTS ( (0,0), (20,0) ) } } PIN 8, 0, 0 { COORD (0,200) VARIABLES { #DIRECTION="OUT" #LENGTH="20" #NAME="Q1" #NUMBER="0" #SIDE="left" } LINE 2, 0, 0 { POINTS ( (20,0), (0,0) ) } } PIN 10, 0, 0 { COORD (0,160) VARIABLES { #DIRECTION="IN" #LENGTH="20" #NAME="D1" #NUMBER="0" #SIDE="left" } LINE 2, 0, 0 { POINTS ( (0,0), (20,0) ) } } PIN 12, 0, 0 { COORD (0,240) VARIABLES { #DIRECTION="OUT" #LENGTH="20" #NAME="Q2" #NUMBER="0" #SIDE="left" } LINE 2, 0, 0 { POINTS ( (20,0), (0,0) ) } } PIN 14, 0, 0 { COORD (0,280) VARIABLES { #DIRECTION="IN" #LENGTH="20" #NAME="D2" #NUMBER="0" #SIDE="left" } LINE 2, 0, 0 { POINTS ( (0,0), (20,0) ) } } PIN 16, 0, 0 { COORD (0,360) VARIABLES { #DIRECTION="OUT" #LENGTH="20" #NAME="Q3" #NUMBER="0" #SIDE="left" } LINE 2, 0, 0 { POINTS ( (20,0), (0,0) ) } } PIN 18, 0, 0 { COORD (0,320) VARIABLES { #DIRECTION="IN" #LENGTH="20" #NAME="D3" #NUMBER="0" #SIDE="left" } LINE 2, 0, 0 { POINTS ( (0,0), (20,0) ) } } PIN 20, 0, 0 { COORD (160,360) VARIABLES { #DIRECTION="OUT" #LENGTH="20" #NAME="Q4" #NUMBER="0" #SIDE="right" } LINE 2, 0, 0 { POINTS ( (-20,0), (0,0) ) } } PIN 22, 0, 0 { COORD (160,320) VARIABLES { #DIRECTION="IN" #LENGTH="20" #NAME="D4" #NUMBER="0" #SIDE="right" } LINE 2, 0, 0 { POINTS ( (0,0), (-20,0) ) } } PIN 24, 0, 0 { COORD (160,240) VARIABLES { #DIRECTION="OUT" #LENGTH="20" #NAME="Q5" #NUMBER="0" #SIDE="right" } LINE 2, 0, 0 { POINTS ( (-20,0), (0,0) ) } } PIN 26, 0, 0 { COORD (160,280) VARIABLES { #DIRECTION="IN" #LENGTH="20" #NAME="D5" #NUMBER="0" #SIDE="right" } LINE 2, 0, 0 { POINTS ( (0,0), (-20,0) ) } } PIN 28, 0, 0 { COORD (160,200) VARIABLES { #DIRECTION="OUT" #LENGTH="20" #NAME="Q6" #NUMBER="0" #SIDE="right" } LINE 2, 0, 0 { POINTS ( (-20,0), (0,0) ) } } PIN 30, 0, 0 { COORD (160,160) VARIABLES { #DIRECTION="IN" #LENGTH="20" #NAME="D6" #NUMBER="0" #SIDE="right" } LINE 2, 0, 0 { POINTS ( (0,0), (-20,0) ) } } PIN 32, 0, 0 { COORD (160,80) VARIABLES { #DIRECTION="OUT" #LENGTH="20" #NAME="Q7" #NUMBER="0" #SIDE="right" } LINE 2, 0, 0 { POINTS ( (-20,0), (0,0) ) } } PIN 34, 0, 0 { COORD (160,120) VARIABLES { #DIRECTION="IN" #LENGTH="20" #NAME="D7" #NUMBER="0" #SIDE="right" } LINE 2, 0, 0 { POINTS ( (0,0), (-20,0) ) } } PIN 36, 0, 0 { COORD (0,40) VARIABLES { #DIRECTION="IN" #LABEL="~In" #LENGTH="20" #NAME="OE" #NUMBER="0" #SIDE="left" #VERILOG_DELAY="" } LINE 1, 0, 0 { OUTLINE 0,1, (0,0,128) POINTS ( (0,0), (12,0) ) } ELLIPSE 2, 0, 0 { OUTLINE 0,1, (0,0,128) AREA (12,-4,20,4) } } PIN 38, 0, 0 { COORD (0,400) VARIABLES { #DIRECTION="IN" #LENGTH="20" #NAME="gndc" #NUMBER="0" #SIDE="left" } LINE 2, 0, 0 { POINTS ( (0,0), (20,0) ) } } PIN 40, 0, 0 { COORD (160,40) VARIABLES { #DIRECTION="IN" #LENGTH="20" #NAME="vddc" #NUMBER="0" #SIDE="right" } LINE 2, 0, 0 { POINTS ( (0,0), (-20,0) ) } } } } } SYMBOL "lib370" "mux2" "mux2" { HEADER { VARIABLES { #DESCRIPTION="" #LANGUAGE="VERILOG" #MODIFIED="1113266909" #NO_SYMBOL_NAME="1" #NO_SYMBOL_REFERENCE="1" } } PAGE "" { PAGEHEADER { RECT (0,0,120,80) FREEID 15 } BODY { TEXT 3, 0, 0 { TEXT "$#NAME" RECT (25,10,44,34) ALIGN 4 MARGINS (1,1) PARENT 2 } TEXT 5, 0, 1 { TEXT "$#NAME" RECT (78,30,95,54) ALIGN 6 MARGINS (1,1) PARENT 4 } TEXT 7, 0, 0 { TEXT "$#NAME" RECT (25,50,44,74) ALIGN 4 MARGINS (1,1) PARENT 6 } TEXT 9, 0, 0 { TEXT "$#NAME" RECT (50,36,65,60) ALIGN 6 MARGINS (1,1) PARENT 8 ORIENTATION 4 } GROUP 14, -1, 0 { RECT (20,0,100,80) VARIABLES { #NAME="BUF" } FREEID 1 LINE 13, 0, 0 { OUTLINE 0,2, (132,4,0) POINTS ( (0,0), (79,39), (0,79), (0,0) ) FILL (0,(255,215,215),0) } } PIN 2, 0, 0 { COORD (0,20) VARIABLES { #DIRECTION="IN" #LENGTH="20" #NAME="I0" #NUMBER="0" } LINE 2, 0, 0 { POINTS ( (0,0), (20,0) ) } } PIN 4, 0, 0 { COORD (120,40) VARIABLES { #DIRECTION="OUT" #LENGTH="20" #NAME="O" #NUMBER="0" #SIDE="right" #VERILOG_TYPE="reg" } LINE 2, 0, 0 { POINTS ( (-20,0), (0,0) ) } } PIN 6, 0, 0 { COORD (0,60) VARIABLES { #DIRECTION="IN" #LENGTH="20" #NAME="I1" #NUMBER="0" } LINE 2, 0, 0 { POINTS ( (0,0), (20,0) ) } } PIN 8, 0, 0 { COORD (60,80) VARIABLES { #DIRECTION="IN" #LENGTH="20" #NAME="S" #NUMBER="0" #SIDE="bottom" } LINE 2, 0, 0 { POINTS ( (0,0), (0,-20) ) } } } } } } PAGE "" { PAGEHEADER { PAGESIZE (2200,1700) MARGINS (200,200,200,200) RECT (0,0,100,200) } BODY { INSTANCE 29, 0, 0 { VARIABLES { #COMPONENT="c74374" #LIBRARY="lib370" #REFERENCE="U1" #SYMBOL="c74374" } COORD (540,1260) ORIENTATION 3 VERTEXES ( (16,465), (18,453), (14,451), (12,467), (8,469), (10,449), (6,567), (4,471), (36,485), (2,487), (20,473), (22,461), (26,459), (24,475), (28,477), (30,457), (34,455), (32,463), (40,483), (38,1003) ) } TEXT 50, 0, 0 { TEXT "$#REFERENCE" RECT (540,1281,579,1316) MARGINS (1,1) PARENT 29 ORIENTATION 3 } INSTANCE 51, 0, 0 { VARIABLES { #COMPONENT="BusInput" #LIBRARY="#terminals" #REFERENCE="EXT(7:0)" #SYMBOL="BusInput" #VERILOG_TYPE="wire" } COORD (360,320) } TEXT 52, 0, 0 { TEXT "$#REFERENCE" RECT (190,303,309,338) ALIGN 6 MARGINS (1,1) PARENT 51 } INSTANCE 53, 0, 0 { VARIABLES { #ARRAY="8" #COMPONENT="mux2" #LIBRARY="lib370" #REFERENCE="U4" #SYMBOL="mux2" } COORD (620,520) VERTEXES ( (2,573), (6,439), (8,447), (4,441) ) } TEXT 58, 0, 0 { TEXT "@INSTANCE_ARRAY" RECT (620,601,647,634) PARENT 53 } TEXT 61, 0, 0 { TEXT "$#NAME" RECT (492,551,588,580) ALIGN 9 MARGINS (1,1) PARENT 582 } NET BUS 63, 0, 0 { VARIABLES { #NAME="A_D(7:0)" #VERILOG_TYPE="wire" } } TEXT 66, 0, 0 { TEXT "$#NAME" RECT (742,530,838,559) ALIGN 9 MARGINS (1,1) PARENT 584 } NET WIRE 67, 0, 0 { VARIABLES { #NAME="FORCE" #VERILOG_TYPE="wire" } } INSTANCE 74, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="FORCE" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (360,380) } TEXT 75, 0, 0 { TEXT "$#REFERENCE" RECT (205,363,309,398) ALIGN 6 MARGINS (1,1) PARENT 74 } NET WIRE 76, 0, 0 { VARIABLES { #NAME="A_D[1]" } } TEXT 78, 0, 0 { TEXT "$#NAME" RECT (456,1066,530,1095) ALIGN 4 MARGINS (1,1) PARENT 595 } NET WIRE 79, 0, 0 { VARIABLES { #NAME="A_D[2]" } } TEXT 81, 0, 0 { TEXT "$#NAME" RECT (457,950,531,979) ALIGN 9 MARGINS (1,1) PARENT 596 } NET WIRE 82, 0, 0 { VARIABLES { #NAME="A_D[3]" } } TEXT 84, 0, 0 { TEXT "$#NAME" RECT (457,910,531,939) ALIGN 9 MARGINS (1,1) PARENT 597 } TEXT 85, 0, 0 { TEXT "$#NAME" RECT (733,1110,807,1139) ALIGN 9 MARGINS (1,1) PARENT 598 } NET WIRE 87, 0, 0 { VARIABLES { #NAME="A_D[7]" } } NET WIRE 88, 0, 0 { VARIABLES { #NAME="A_D[6]" } } TEXT 90, 0, 0 { TEXT "$#NAME" RECT (733,1070,807,1099) ALIGN 9 MARGINS (1,1) PARENT 599 } NET WIRE 91, 0, 0 { VARIABLES { #NAME="A_D[5]" } } TEXT 93, 0, 0 { TEXT "$#NAME" RECT (733,950,807,979) ALIGN 9 MARGINS (1,1) PARENT 600 } NET WIRE 94, 0, 0 { VARIABLES { #NAME="A_D[4]" } } TEXT 96, 0, 0 { TEXT "$#NAME" RECT (733,910,807,939) ALIGN 9 MARGINS (1,1) PARENT 601 } NET WIRE 97, 0, 0 { VARIABLES { #NAME="A_OUT[7]" #VERILOG_TYPE="wire" } } NET WIRE 99, 0, 0 { VARIABLES { #NAME="A_OUT[3]" } } TEXT 101, 0, 0 { TEXT "$#NAME" RECT (448,870,555,899) ALIGN 9 MARGINS (1,1) PARENT 603 } NET WIRE 102, 0, 0 { VARIABLES { #NAME="A_OUT[2]" } } TEXT 104, 0, 0 { TEXT "$#NAME" RECT (448,990,555,1019) ALIGN 9 MARGINS (1,1) PARENT 604 } NET WIRE 105, 0, 0 { VARIABLES { #NAME="A_OUT[1]" } } TEXT 107, 0, 0 { TEXT "$#NAME" RECT (448,1030,555,1059) ALIGN 9 MARGINS (1,1) PARENT 605 } NET WIRE 108, 0, 0 { VARIABLES { #NAME="A_OUT[0]" } } TEXT 110, 0, 0 { TEXT "$#NAME" RECT (448,1150,555,1179) ALIGN 9 MARGINS (1,1) PARENT 606 } NET WIRE 111, 0, 0 { VARIABLES { #NAME="A_OUT[4]" } } TEXT 113, 0, 0 { TEXT "$#NAME" RECT (717,870,824,899) ALIGN 9 MARGINS (1,1) PARENT 607 } NET WIRE 114, 0, 0 { VARIABLES { #NAME="A_OUT[5]" } } TEXT 116, 0, 0 { TEXT "$#NAME" RECT (717,990,824,1019) ALIGN 9 MARGINS (1,1) PARENT 608 } NET WIRE 117, 0, 0 { VARIABLES { #NAME="A_OUT[6]" } } TEXT 119, 0, 0 { TEXT "$#NAME" RECT (717,1030,824,1059) ALIGN 9 MARGINS (1,1) PARENT 609 } TEXT 120, 0, 0 { TEXT "$#NAME" RECT (717,1150,824,1179) ALIGN 9 MARGINS (1,1) PARENT 602 } INSTANCE 121, 0, 0 { VARIABLES { #COMPONENT="Power" #LIBRARY="#connectors" #REFERENCE="VCC" #SYMBOL="Power" } COORD (1460,280) } TEXT 122, 0, 0 { TEXT "$#REFERENCE" RECT (1471,233,1534,268) ALIGN 4 MARGINS (1,1) PARENT 121 } NET WIRE 123, 0, 0 { VARIABLES { #NAME="VCC" } } TEXT 127, 0, 0 { TEXT "$#NAME" RECT (740,1190,791,1219) ALIGN 9 MARGINS (1,1) PARENT 612 } TEXT 128, 0, 0 { TEXT "$#NAME" RECT (450,1190,505,1219) ALIGN 9 MARGINS (1,1) PARENT 613 } NET WIRE 130, 0, 0 { VARIABLES { #NAME="Shift" #VERILOG_TYPE="wire" } } TEXT 137, 0, 0 { TEXT "$#NAME" RECT (762,776,813,805) ALIGN 4 MARGINS (1,1) PARENT 616 } INSTANCE 138, 0, 0 { VARIABLES { #COMPONENT="Input" #LIBRARY="#terminals" #REFERENCE="Shift" #SYMBOL="Input" #VERILOG_TYPE="wire" } COORD (360,520) } TEXT 139, 0, 0 { TEXT "$#REFERENCE" RECT (249,503,309,538) ALIGN 6 MARGINS (1,1) PARENT 138 } INSTANCE 140, 0, 0 { VARIABLES { #COMPONENT="BusOutput" #LIBRARY="#terminals" #REFERENCE="A_OUT(7:0)" #SYMBOL="BusOutput" #VERILOG_TYPE="wire" } COORD (1680,300) } TEXT 141, 0, 0 { TEXT "$#REFERENCE" RECT (1732,283,1892,318) ALIGN 4 MARGINS (1,1) PARENT 140 } INSTANCE 142, 0, 0 { VARIABLES { #COMPONENT="c74374" #LIBRARY="lib370" #REFERENCE="U2" #SYMBOL="c74374" } COORD (1060,1260) ORIENTATION 3 VERTEXES ( (16,507), (18,497), (14,495), (12,509), (8,511), (10,493), (6,559), (4,513), (36,523), (2,489), (20,515), (22,505), (26,503), (24,517), (28,519), (30,501), (34,499), (32,521), (40,800), (38,982) ) } TEXT 163, 0, 0 { TEXT "$#REFERENCE" RECT (1060,1281,1099,1316) MARGINS (1,1) PARENT 142 ORIENTATION 3 } TEXT 164, 0, 0 { TEXT "$#NAME" RECT (976,1066,1051,1095) ALIGN 4 MARGINS (1,1) PARENT 623 } TEXT 166, 0, 0 { TEXT "$#NAME" RECT (977,950,1052,979) ALIGN 9 MARGINS (1,1) PARENT 624 } TEXT 168, 0, 0 { TEXT "$#NAME" RECT (977,910,1052,939) ALIGN 9 MARGINS (1,1) PARENT 625 } TEXT 170, 0, 0 { TEXT "$#NAME" RECT (1253,1110,1328,1139) ALIGN 9 MARGINS (1,1) PARENT 626 } TEXT 172, 0, 0 { TEXT "$#NAME" RECT (1253,1070,1328,1099) ALIGN 9 MARGINS (1,1) PARENT 627 } TEXT 174, 0, 0 { TEXT "$#NAME" RECT (1253,950,1328,979) ALIGN 9 MARGINS (1,1) PARENT 628 } TEXT 176, 0, 0 { TEXT "$#NAME" RECT (1253,910,1328,939) ALIGN 9 MARGINS (1,1) PARENT 629 } TEXT 178, 0, 0 { TEXT "$#NAME" RECT (967,870,1075,899) ALIGN 9 MARGINS (1,1) PARENT 630 } TEXT 180, 0, 0 { TEXT "$#NAME" RECT (967,990,1075,1019) ALIGN 9 MARGINS (1,1) PARENT 631 } TEXT 182, 0, 0 { TEXT "$#NAME" RECT (967,1030,1075,1059) ALIGN 9 MARGINS (1,1) PARENT 632 } TEXT 184, 0, 0 { TEXT "$#NAME" RECT (967,1150,1075,1179) ALIGN 9 MARGINS (1,1) PARENT 633 } TEXT 186, 0, 0 { TEXT "$#NAME" RECT (1236,870,1344,899) ALIGN 9 MARGINS (1,1) PARENT 634 } TEXT 188, 0, 0 { TEXT "$#NAME" RECT (1236,990,1344,1019) ALIGN 9 MARGINS (1,1) PARENT 635 } TEXT 190, 0, 0 { TEXT "$#NAME" RECT (1236,1030,1344,1059) ALIGN 9 MARGINS (1,1) PARENT 636 } TEXT 192, 0, 0 { TEXT "$#NAME" RECT (1236,1150,1344,1179) ALIGN 9 MARGINS (1,1) PARENT 637 } TEXT 194, 0, 0 { TEXT "$#NAME" RECT (1260,1190,1311,1219) ALIGN 9 MARGINS (1,1) PARENT 802 } TEXT 195, 0, 0 { TEXT "$#NAME" RECT (967,1190,1022,1219) ALIGN 9 MARGINS (1,1) PARENT 638 } TEXT 197, 0, 0 { TEXT "$#NAME" RECT (1282,776,1333,805) ALIGN 4 MARGINS (1,1) PARENT 619 } INSTANCE 198, 0, 0 { VARIABLES { #COMPONENT="c74374" #LIBRARY="lib370" #REFERENCE="U3" #SYMBOL="c74374" } COORD (1580,1260) ORIENTATION 3 VERTEXES ( (16,541), (18,531), (14,529), (12,543), (8,545), (10,525), (6,527), (2,491), (20,549), (22,539), (26,537), (24,551), (28,553), (30,535), (34,533), (32,555), (36,769), (40,803), (4,835), (38,996) ) } TEXT 219, 0, 0 { TEXT "$#REFERENCE" RECT (1580,1281,1619,1316) MARGINS (1,1) PARENT 198 ORIENTATION 3 } TEXT 220, 0, 0 { TEXT "$#NAME" RECT (1482,1066,1558,1095) ALIGN 4 MARGINS (1,1) PARENT 639 } TEXT 222, 0, 0 { TEXT "$#NAME" RECT (1482,1111,1558,1140) ALIGN 9 MARGINS (1,1) PARENT 640 } TEXT 224, 0, 0 { TEXT "$#NAME" RECT (1483,950,1559,979) ALIGN 9 MARGINS (1,1) PARENT 641 } TEXT 226, 0, 0 { TEXT "$#NAME" RECT (1483,910,1559,939) ALIGN 9 MARGINS (1,1) PARENT 642 } TEXT 228, 0, 0 { TEXT "$#NAME" RECT (1772,1110,1848,1139) ALIGN 9 MARGINS (1,1) PARENT 643 } TEXT 230, 0, 0 { TEXT "$#NAME" RECT (1772,1070,1848,1099) ALIGN 9 MARGINS (1,1) PARENT 644 } TEXT 232, 0, 0 { TEXT "$#NAME" RECT (1772,950,1848,979) ALIGN 9 MARGINS (1,1) PARENT 645 } TEXT 234, 0, 0 { TEXT "$#NAME" RECT (1772,910,1848,939) ALIGN 9 MARGINS (1,1) PARENT 646 } TEXT 236, 0, 0 { TEXT "$#NAME" RECT (1472,870,1581,899) ALIGN 9 MARGINS (1,1) PARENT 647 } TEXT 238, 0, 0 { TEXT "$#NAME" RECT (1472,990,1581,1019) ALIGN 9 MARGINS (1,1) PARENT 648 } TEXT 240, 0, 0 { TEXT "$#NAME" RECT (1472,1030,1581,1059) ALIGN 9 MARGINS (1,1) PARENT 649 } TEXT 244, 0, 0 { TEXT "$#NAME" RECT (1756,870,1865,899) ALIGN 9 MARGINS (1,1) PARENT 655 } TEXT 246, 0, 0 { TEXT "$#NAME" RECT (1756,990,1865,1019) ALIGN 9 MARGINS (1,1) PARENT 656 } TEXT 248, 0, 0 { TEXT "$#NAME" RECT (1756,1030,1865,1059) ALIGN 9 MARGINS (1,1) PARENT 657 } TEXT 250, 0, 0 { TEXT "$#NAME" RECT (1756,1150,1865,1179) ALIGN 9 MARGINS (1,1) PARENT 658 } TEXT 252, 0, 0 { TEXT "$#NAME" RECT (1780,1190,1831,1219) ALIGN 9 MARGINS (1,1) PARENT 805 } TEXT 253, 0, 0 { TEXT "$#NAME" RECT (1472,1190,1527,1219) ALIGN 9 MARGINS (1,1) PARENT 771 } TEXT 255, 0, 0 { TEXT "$#NAME" RECT (1802,776,1853,805) ALIGN 4 MARGINS (1,1) PARENT 622 } NET WIRE 256, 0, 0 { VARIABLES { #NAME="B_D[7]" } } NET WIRE 257, 0, 0 { VARIABLES { #NAME="B_D[6]" } } NET WIRE 258, 0, 0 { VARIABLES { #NAME="B_D[5]" } } NET WIRE 259, 0, 0 { VARIABLES { #NAME="B_D[4]" } } NET WIRE 260, 0, 0 { VARIABLES { #NAME="B_OUT[4]" } } NET WIRE 261, 0, 0 { VARIABLES { #NAME="B_OUT[5]" } } NET WIRE 262, 0, 0 { VARIABLES { #NAME="B_OUT[6]" } } NET WIRE 263, 0, 0 { VARIABLES { #NAME="B_OUT[7]" } } NET WIRE 264, 0, 0 { VARIABLES { #NAME="C_D[7]" } } NET WIRE 265, 0, 0 { VARIABLES { #NAME="C_D[6]" } } NET WIRE 266, 0, 0 { VARIABLES { #NAME="C_D[5]" } } NET WIRE 267, 0, 0 { VARIABLES { #NAME="C_D[4]" } } NET WIRE 268, 0, 0 { VARIABLES { #NAME="C_OUT[4]" } } NET WIRE 269, 0, 0 { VARIABLES { #NAME="C_OUT[5]" } } NET WIRE 270, 0, 0 { VARIABLES { #NAME="C_OUT[6]" } } NET WIRE 271, 0, 0 { VARIABLES { #NAME="C_OUT[7]" #VERILOG_TYPE="wire" } } NET WIRE 272, 0, 0 { VARIABLES { #NAME="B_OUT[3]" } } NET WIRE 273, 0, 0 { VARIABLES { #NAME="B_D[3]" } } NET WIRE 274, 0, 0 { VARIABLES { #NAME="B_D[2]" } } NET WIRE 275, 0, 0 { VARIABLES { #NAME="B_OUT[2]" } } NET WIRE 276, 0, 0 { VARIABLES { #NAME="B_OUT[1]" } } NET WIRE 277, 0, 0 { VARIABLES { #NAME="B_D[1]" } } NET WIRE 278, 0, 0 { VARIABLES { #NAME="B_D[0]" } } TEXT 280, 0, 0 { TEXT "$#NAME" RECT (977,1110,1052,1139) ALIGN 9 MARGINS (1,1) PARENT 660 } NET WIRE 281, 0, 0 { VARIABLES { #NAME="B_OUT[0]" } } NET WIRE 282, 0, 0 { VARIABLES { #NAME="C_OUT[3]" } } NET WIRE 283, 0, 0 { VARIABLES { #NAME="C_D[3]" } } NET WIRE 284, 0, 0 { VARIABLES { #NAME="C_D[2]" } } NET WIRE 285, 0, 0 { VARIABLES { #NAME="C_OUT[2]" } } NET WIRE 286, 0, 0 { VARIABLES { #NAME="C_OUT[1]" } } NET WIRE 287, 0, 0 { VARIABLES { #NAME="C_D[1]" } } NET WIRE 288, 0, 0 { VARIABLES { #NAME="C_D[0]" } } INSTANCE 292, 0, 0 { VARIABLES { #ARRAY="8" #COMPONENT="mux2" #LIBRARY="lib370" #REFERENCE="U5" #SYMBOL="mux2" } COORD (1120,520) VERTEXES ( (2,577), (8,445), (4,561), (6,709) ) } TEXT 297, 0, 0 { TEXT "@INSTANCE_ARRAY" RECT (1120,601,1147,634) PARENT 292 } TEXT 298, 0, 0 { TEXT "$#NAME" RECT (992,551,1088,580) ALIGN 9 MARGINS (1,1) PARENT 711 } TEXT 299, 0, 0 { TEXT "$#NAME" RECT (1244,530,1341,559) ALIGN 9 MARGINS (1,1) PARENT 662 } INSTANCE 301, 0, 0 { VARIABLES { #ARRAY="8" #COMPONENT="mux2" #LIBRARY="lib370" #REFERENCE="U6" #SYMBOL="mux2" } COORD (1640,520) VERTEXES ( (2,579), (6,563), (8,443), (4,565) ) } TEXT 306, 0, 0 { TEXT "@INSTANCE_ARRAY" RECT (1640,601,1667,634) PARENT 301 } TEXT 307, 0, 0 { TEXT "$#NAME" RECT (1552,551,1648,580) ALIGN 9 MARGINS (1,1) PARENT 664 } TEXT 309, 0, 0 { TEXT "$#NAME" RECT (1763,530,1861,559) ALIGN 9 MARGINS (1,1) PARENT 666 } NET BUS 311, 0, 0 { VARIABLES { #NAME="B_D(7:0)" #VERILOG_TYPE="wire" } } NET BUS 313, 0, 0 { VARIABLES { #NAME="C_D(7:0)" #VERILOG_TYPE="wire" } } INSTANCE 315, 0, 0 { VARIABLES { #COMPONENT="BusOutput" #LIBRARY="#terminals" #REFERENCE="B_OUT(7:0)" #SYMBOL="BusOutput" #VERILOG_TYPE="wire" } COORD (1680,340) } TEXT 316, 0, 0 { TEXT "$#REFERENCE" RECT (1732,323,1892,358) ALIGN 4 MARGINS (1,1) PARENT 315 } INSTANCE 317, 0, 0 { VARIABLES { #COMPONENT="BusOutput" #LIBRARY="#terminals" #REFERENCE="C_OUT(7:0)" #SYMBOL="BusOutput" #VERILOG_TYPE="wire" } COORD (1680,380) } TEXT 318, 0, 0 { TEXT "$#REFERENCE" RECT (1732,363,1894,398) ALIGN 4 MARGINS (1,1) PARENT 317 } TEXT 319, 0, 0 { TEXT "$#NAME" RECT (567,630,653,659) ALIGN 9 MARGINS (1,1) PARENT 594 } TEXT 320, 0, 0 { TEXT "$#NAME" RECT (1067,630,1153,659) ALIGN 9 MARGINS (1,1) PARENT 591 } TEXT 321, 0, 0 { TEXT "$#NAME" RECT (1587,630,1673,659) ALIGN 9 MARGINS (1,1) PARENT 588 } NET BUS 322, 0, 0 { VARIABLES { #NAME="EXT(7:0)" #VERILOG_TYPE="wire" } } NET WIRE 323, 0, 0 { VARIABLES { #NAME="A_D[0]" } } TEXT 325, 0, 0 { TEXT "$#NAME" RECT (443,1110,517,1139) ALIGN 9 MARGINS (1,1) PARENT 668 } NET BUS 357, 0, 0 NET BUS 379, 0, 0 NET BUS 417, 0, 0 VTX 439, 0, 0 { COORD (620,580) } VTX 440, 0, 0 { COORD (500,580) } VTX 441, 0, 0 { COORD (740,560) } VTX 442, 0, 0 { COORD (760,680) } VTX 443, 0, 0 { COORD (1700,600) } VTX 444, 0, 0 { COORD (1560,660) } VTX 445, 0, 0 { COORD (1180,600) } VTX 446, 0, 0 { COORD (1040,660) } VTX 447, 0, 0 { COORD (680,600) } VTX 448, 0, 0 { COORD (540,660) } VTX 449, 0, 0 { COORD (540,1100) } VTX 450, 0, 0 { COORD (420,1100) } VTX 451, 0, 0 { COORD (540,980) } VTX 452, 0, 0 { COORD (420,980) } VTX 453, 0, 0 { COORD (540,940) } VTX 454, 0, 0 { COORD (420,940) } VTX 455, 0, 0 { COORD (700,1140) } VTX 456, 0, 0 { COORD (840,1140) } VTX 457, 0, 0 { COORD (700,1100) } VTX 458, 0, 0 { COORD (840,1100) } VTX 459, 0, 0 { COORD (700,980) } VTX 460, 0, 0 { COORD (840,980) } VTX 461, 0, 0 { COORD (700,940) } VTX 462, 0, 0 { COORD (840,940) } VTX 463, 0, 0 { COORD (700,1180) } VTX 464, 0, 0 { COORD (840,1180) } VTX 465, 0, 0 { COORD (540,900) } VTX 466, 0, 0 { COORD (420,900) } VTX 467, 0, 0 { COORD (540,1020) } VTX 468, 0, 0 { COORD (420,1020) } VTX 469, 0, 0 { COORD (540,1060) } VTX 470, 0, 0 { COORD (420,1060) } VTX 471, 0, 0 { COORD (540,1180) } VTX 472, 0, 0 { COORD (420,1180) } VTX 473, 0, 0 { COORD (700,900) } VTX 474, 0, 0 { COORD (840,900) } VTX 475, 0, 0 { COORD (700,1020) } VTX 476, 0, 0 { COORD (840,1020) } VTX 477, 0, 0 { COORD (700,1060) } VTX 478, 0, 0 { COORD (840,1060) } VTX 483, 0, 0 { COORD (700,1220) } VTX 484, 0, 0 { COORD (840,1220) } VTX 485, 0, 0 { COORD (540,1220) } VTX 486, 0, 0 { COORD (420,1220) } VTX 487, 0, 0 { COORD (700,860) } VTX 488, 0, 0 { COORD (760,720) } VTX 489, 0, 0 { COORD (1220,860) } VTX 490, 0, 0 { COORD (1280,720) } VTX 491, 0, 0 { COORD (1740,860) } VTX 492, 0, 0 { COORD (1800,720) } VTX 493, 0, 0 { COORD (1060,1100) } VTX 494, 0, 0 { COORD (940,1100) } VTX 495, 0, 0 { COORD (1060,980) } VTX 496, 0, 0 { COORD (940,980) } VTX 497, 0, 0 { COORD (1060,940) } VTX 498, 0, 0 { COORD (940,940) } VTX 499, 0, 0 { COORD (1220,1140) } VTX 500, 0, 0 { COORD (1360,1140) } VTX 501, 0, 0 { COORD (1220,1100) } VTX 502, 0, 0 { COORD (1360,1100) } VTX 503, 0, 0 { COORD (1220,980) } VTX 504, 0, 0 { COORD (1360,980) } VTX 505, 0, 0 { COORD (1220,940) } VTX 506, 0, 0 { COORD (1360,940) } VTX 507, 0, 0 { COORD (1060,900) } VTX 508, 0, 0 { COORD (940,900) } VTX 509, 0, 0 { COORD (1060,1020) } VTX 510, 0, 0 { COORD (940,1020) } VTX 511, 0, 0 { COORD (1060,1060) } VTX 512, 0, 0 { COORD (940,1060) } VTX 513, 0, 0 { COORD (1060,1180) } VTX 514, 0, 0 { COORD (940,1180) } VTX 515, 0, 0 { COORD (1220,900) } VTX 516, 0, 0 { COORD (1360,900) } VTX 517, 0, 0 { COORD (1220,1020) } VTX 518, 0, 0 { COORD (1360,1020) } VTX 519, 0, 0 { COORD (1220,1060) } VTX 520, 0, 0 { COORD (1360,1060) } VTX 521, 0, 0 { COORD (1220,1180) } VTX 522, 0, 0 { COORD (1360,1180) } VTX 523, 0, 0 { COORD (1060,1220) } VTX 524, 0, 0 { COORD (940,1220) } VTX 525, 0, 0 { COORD (1580,1100) } VTX 526, 0, 0 { COORD (1440,1100) } VTX 527, 0, 0 { COORD (1580,1140) } VTX 528, 0, 0 { COORD (1440,1140) } VTX 529, 0, 0 { COORD (1580,980) } VTX 530, 0, 0 { COORD (1440,980) } VTX 531, 0, 0 { COORD (1580,940) } VTX 532, 0, 0 { COORD (1440,940) } VTX 533, 0, 0 { COORD (1740,1140) } VTX 534, 0, 0 { COORD (1880,1140) } VTX 535, 0, 0 { COORD (1740,1100) } VTX 536, 0, 0 { COORD (1880,1100) } VTX 537, 0, 0 { COORD (1740,980) } VTX 538, 0, 0 { COORD (1880,980) } VTX 539, 0, 0 { COORD (1740,940) } VTX 540, 0, 0 { COORD (1880,940) } VTX 541, 0, 0 { COORD (1580,900) } VTX 542, 0, 0 { COORD (1440,900) } VTX 543, 0, 0 { COORD (1580,1020) } VTX 544, 0, 0 { COORD (1440,1020) } VTX 545, 0, 0 { COORD (1580,1060) } VTX 546, 0, 0 { COORD (1440,1060) } VTX 549, 0, 0 { COORD (1740,900) } VTX 550, 0, 0 { COORD (1880,900) } VTX 551, 0, 0 { COORD (1740,1020) } VTX 552, 0, 0 { COORD (1880,1020) } VTX 553, 0, 0 { COORD (1740,1060) } VTX 554, 0, 0 { COORD (1880,1060) } VTX 555, 0, 0 { COORD (1740,1180) } VTX 556, 0, 0 { COORD (1880,1180) } VTX 559, 0, 0 { COORD (1060,1140) } VTX 560, 0, 0 { COORD (940,1140) } VTX 561, 0, 0 { COORD (1240,560) } VTX 562, 0, 0 { COORD (1280,680) } VTX 563, 0, 0 { COORD (1640,580) } VTX 564, 0, 0 { COORD (1520,580) } VTX 565, 0, 0 { COORD (1760,560) } VTX 566, 0, 0 { COORD (1800,660) } VTX 567, 0, 0 { COORD (540,1140) } VTX 568, 0, 0 { COORD (420,1140) } VTX 573, 0, 0 { COORD (620,540) } VTX 574, 0, 0 { COORD (500,540) } VTX 577, 0, 0 { COORD (1120,540) } VTX 578, 0, 0 { COORD (1000,540) } VTX 579, 0, 0 { COORD (1640,540) } VTX 580, 0, 0 { COORD (1520,540) } BUS 582, 0, 0 { NET 322 VTX 439, 440 VARIABLES { #NAMED="1" } } VTX 583, 0, 0 { COORD (760,560) } BUS 584, 0, 0 { NET 63 VTX 441, 583 VARIABLES { #NAMED="1" } } BUS 585, 0, 0 { NET 63 VTX 583, 442 } VTX 586, 0, 0 { COORD (1700,660) } WIRE 587, 0, 0 { NET 67 VTX 443, 586 } WIRE 588, 0, 0 { NET 67 VTX 586, 444 VARIABLES { #NAMED="1" } } VTX 589, 0, 0 { COORD (1180,660) } WIRE 590, 0, 0 { NET 67 VTX 445, 589 } WIRE 591, 0, 0 { NET 67 VTX 589, 446 VARIABLES { #NAMED="1" } } VTX 592, 0, 0 { COORD (680,660) } WIRE 593, 0, 0 { NET 67 VTX 447, 592 } WIRE 594, 0, 0 { NET 67 VTX 592, 448 VARIABLES { #NAMED="1" } } WIRE 595, 0, 0 { NET 76 VTX 449, 450 VARIABLES { #NAMED="1" } } WIRE 596, 0, 0 { NET 79 VTX 451, 452 VARIABLES { #NAMED="1" } } WIRE 597, 0, 0 { NET 82 VTX 453, 454 VARIABLES { #NAMED="1" } } WIRE 598, 0, 0 { NET 87 VTX 455, 456 VARIABLES { #NAMED="1" } } WIRE 599, 0, 0 { NET 88 VTX 457, 458 VARIABLES { #NAMED="1" } } WIRE 600, 0, 0 { NET 91 VTX 459, 460 VARIABLES { #NAMED="1" } } WIRE 601, 0, 0 { NET 94 VTX 461, 462 VARIABLES { #NAMED="1" } } WIRE 602, 0, 0 { NET 97 VTX 463, 464 VARIABLES { #NAMED="1" } } WIRE 603, 0, 0 { NET 99 VTX 465, 466 VARIABLES { #NAMED="1" } } WIRE 604, 0, 0 { NET 102 VTX 467, 468 VARIABLES { #NAMED="1" } } WIRE 605, 0, 0 { NET 105 VTX 469, 470 VARIABLES { #NAMED="1" } } WIRE 606, 0, 0 { NET 108 VTX 471, 472 VARIABLES { #NAMED="1" } } WIRE 607, 0, 0 { NET 111 VTX 473, 474 VARIABLES { #NAMED="1" } } WIRE 608, 0, 0 { NET 114 VTX 475, 476 VARIABLES { #NAMED="1" } } WIRE 609, 0, 0 { NET 117 VTX 477, 478 VARIABLES { #NAMED="1" } } WIRE 612, 0, 0 { NET 123 VTX 483, 484 VARIABLES { #NAMED="1" } } WIRE 613, 0, 0 { NET 768 VTX 485, 486 VARIABLES { #NAMED="1" } } VTX 614, 0, 0 { COORD (760,860) } WIRE 615, 0, 0 { NET 130 VTX 487, 614 } WIRE 616, 0, 0 { NET 130 VTX 614, 488 VARIABLES { #NAMED="1" } } VTX 617, 0, 0 { COORD (1280,860) } WIRE 618, 0, 0 { NET 130 VTX 489, 617 } WIRE 619, 0, 0 { NET 130 VTX 617, 490 VARIABLES { #NAMED="1" } } VTX 620, 0, 0 { COORD (1800,860) } WIRE 621, 0, 0 { NET 130 VTX 491, 620 } WIRE 622, 0, 0 { NET 130 VTX 620, 492 VARIABLES { #NAMED="1" } } WIRE 623, 0, 0 { NET 277 VTX 493, 494 VARIABLES { #NAMED="1" } } WIRE 624, 0, 0 { NET 274 VTX 495, 496 VARIABLES { #NAMED="1" } } WIRE 625, 0, 0 { NET 273 VTX 497, 498 VARIABLES { #NAMED="1" } } WIRE 626, 0, 0 { NET 256 VTX 499, 500 VARIABLES { #NAMED="1" } } WIRE 627, 0, 0 { NET 257 VTX 501, 502 VARIABLES { #NAMED="1" } } WIRE 628, 0, 0 { NET 258 VTX 503, 504 VARIABLES { #NAMED="1" } } WIRE 629, 0, 0 { NET 259 VTX 505, 506 VARIABLES { #NAMED="1" } } WIRE 630, 0, 0 { NET 272 VTX 507, 508 VARIABLES { #NAMED="1" } } WIRE 631, 0, 0 { NET 275 VTX 509, 510 VARIABLES { #NAMED="1" } } WIRE 632, 0, 0 { NET 276 VTX 511, 512 VARIABLES { #NAMED="1" } } WIRE 633, 0, 0 { NET 281 VTX 513, 514 VARIABLES { #NAMED="1" } } WIRE 634, 0, 0 { NET 260 VTX 515, 516 VARIABLES { #NAMED="1" } } WIRE 635, 0, 0 { NET 261 VTX 517, 518 VARIABLES { #NAMED="1" } } WIRE 636, 0, 0 { NET 262 VTX 519, 520 VARIABLES { #NAMED="1" } } WIRE 637, 0, 0 { NET 263 VTX 521, 522 VARIABLES { #NAMED="1" } } WIRE 638, 0, 0 { NET 768 VTX 523, 524 VARIABLES { #NAMED="1" } } WIRE 639, 0, 0 { NET 287 VTX 525, 526 VARIABLES { #NAMED="1" } } WIRE 640, 0, 0 { NET 288 VTX 527, 528 VARIABLES { #NAMED="1" } } WIRE 641, 0, 0 { NET 284 VTX 529, 530 VARIABLES { #NAMED="1" } } WIRE 642, 0, 0 { NET 283 VTX 531, 532 VARIABLES { #NAMED="1" } } WIRE 643, 0, 0 { NET 264 VTX 533, 534 VARIABLES { #NAMED="1" } } WIRE 644, 0, 0 { NET 265 VTX 535, 536 VARIABLES { #NAMED="1" } } WIRE 645, 0, 0 { NET 266 VTX 537, 538 VARIABLES { #NAMED="1" } } WIRE 646, 0, 0 { NET 267 VTX 539, 540 VARIABLES { #NAMED="1" } } WIRE 647, 0, 0 { NET 282 VTX 541, 542 VARIABLES { #NAMED="1" } } WIRE 648, 0, 0 { NET 285 VTX 543, 544 VARIABLES { #NAMED="1" } } WIRE 649, 0, 0 { NET 286 VTX 545, 546 VARIABLES { #NAMED="1" } } WIRE 655, 0, 0 { NET 268 VTX 549, 550 VARIABLES { #NAMED="1" } } WIRE 656, 0, 0 { NET 269 VTX 551, 552 VARIABLES { #NAMED="1" } } WIRE 657, 0, 0 { NET 270 VTX 553, 554 VARIABLES { #NAMED="1" } } WIRE 658, 0, 0 { NET 271 VTX 555, 556 VARIABLES { #NAMED="1" } } WIRE 660, 0, 0 { NET 278 VTX 559, 560 VARIABLES { #NAMED="1" } } VTX 661, 0, 0 { COORD (1280,560) } BUS 662, 0, 0 { NET 311 VTX 561, 661 VARIABLES { #NAMED="1" } } BUS 663, 0, 0 { NET 311 VTX 661, 562 } BUS 664, 0, 0 { NET 322 VTX 563, 564 VARIABLES { #NAMED="1" } } VTX 665, 0, 0 { COORD (1800,560) } BUS 666, 0, 0 { NET 313 VTX 565, 665 VARIABLES { #NAMED="1" } } BUS 667, 0, 0 { NET 313 VTX 665, 566 } WIRE 668, 0, 0 { NET 323 VTX 567, 568 VARIABLES { #NAMED="1" } } BUS 675, 0, 0 { NET 357 VTX 573, 574 } BUS 679, 0, 0 { NET 379 VTX 577, 578 } BUS 680, 0, 0 { NET 417 VTX 579, 580 } VTX 709, 0, 0 { COORD (1120,580) } VTX 710, 0, 0 { COORD (1000,580) } BUS 711, 0, 0 { NET 322 VTX 709, 710 VARIABLES { #NAMED="1" } } NET WIRE 768, 0, 0 { VARIABLES { #NAME="GND" #VERILOG_TYPE="supply0" } } VTX 769, 0, 0 { COORD (1580,1220) } VTX 770, 0, 0 { COORD (1440,1220) } WIRE 771, 0, 0 { NET 768 VTX 769, 770 VARIABLES { #NAMED="1" } } VTX 800, 0, 0 { COORD (1220,1220) } VTX 801, 0, 0 { COORD (1360,1220) } WIRE 802, 0, 0 { NET 123 VTX 800, 801 VARIABLES { #NAMED="1" } } VTX 803, 0, 0 { COORD (1740,1220) } VTX 804, 0, 0 { COORD (1880,1220) } WIRE 805, 0, 0 { NET 123 VTX 803, 804 VARIABLES { #NAMED="1" } } VTX 835, 0, 0 { COORD (1580,1180) } VTX 836, 0, 0 { COORD (1440,1180) } WIRE 838, 0, 0 { NET 839 VTX 835, 836 VARIABLES { #NAMED="1" } } NET WIRE 839, 0, 0 { VARIABLES { #NAME="C_OUT[0]" } } TEXT 840, 0, 0 { TEXT "$#NAME" RECT (1456,1150,1565,1179) ALIGN 9 MARGINS (1,1) PARENT 838 } VTX 982, 0, 0 { COORD (1060,860) } VTX 983, 0, 0 { COORD (940,860) } WIRE 984, 0, 0 { NET 768 VTX 982, 983 VARIABLES { #NAMED="1" } } TEXT 985, 0, 0 { TEXT "$#NAME" RECT (973,830,1028,859) ALIGN 9 MARGINS (1,1) PARENT 984 } VTX 996, 0, 0 { COORD (1580,860) } VTX 997, 0, 0 { COORD (1440,860) } WIRE 998, 0, 0 { NET 768 VTX 996, 997 VARIABLES { #NAMED="1" } } TEXT 999, 0, 0 { TEXT "$#NAME" RECT (1483,830,1538,859) ALIGN 9 MARGINS (1,1) PARENT 998 } VTX 1003, 0, 0 { COORD (540,860) } VTX 1004, 0, 0 { COORD (420,860) } WIRE 1005, 0, 0 { NET 768 VTX 1003, 1004 VARIABLES { #NAMED="1" } } TEXT 1006, 0, 0 { TEXT "$#NAME" RECT (453,830,508,859) ALIGN 9 MARGINS (1,1) PARENT 1005 } INSTANCE 1010, 0, 0 { VARIABLES { #COMPONENT="Ground" #LIBRARY="#connectors" #REFERENCE="GND" #SYMBOL="Ground" #VERILOG_TYPE="supply0" } COORD (860,1400) VERTEXES ( (2,1015) ) } TEXT 1011, 0, 0 { TEXT "$#REFERENCE" RECT (882,1413,949,1448) ALIGN 4 MARGINS (1,1) PARENT 1010 } VTX 1015, 0, 0 { COORD (860,1400) } VTX 1016, 0, 0 { COORD (860,1380) } WIRE 1018, 0, 0 { NET 768 VTX 1015, 1016 } VTX 1019, 0, 0 { COORD (980,1380) } WIRE 1020, 0, 0 { NET 768 VTX 1016, 1019 VARIABLES { #NAMED="1" } } TEXT 1021, 0, 0 { TEXT "$#NAME" RECT (893,1350,948,1379) ALIGN 9 MARGINS (1,1) PARENT 1020 } } } PAGE "" { PAGEHEADER { PAGESIZE (2200,1700) MARGINS (200,200,200,200) RECT (0,0,0,0) VARIABLES { #ARCHITECTURE="\\#TABLE\\" #BLOCKTABLE_PAGE="1" #BLOCKTABLE_TEMPL="1" #BLOCKTABLE_VISIBLE="0" #ENTITY="\\#TABLE\\" #MODIFIED="1076616772" } } BODY { TEXT 1054, 0, 0 { PAGEALIGN 10 OUTLINE 5,1, (0,0,0) TEXT "Created:" RECT (1140,1386,1257,1439) ALIGN 4 MARGINS (1,10) COLOR (0,0,0) FONT (12,0,0,700,0,0,0,"Arial") } TEXT 1055, 0, 0 { PAGEALIGN 10 TEXT "$CREATIONDATE" RECT (1310,1380,1980,1440) ALIGN 4 MARGINS (1,1) COLOR (0,0,0) FONT (12,0,0,700,0,128,0,"Arial") UPDATE 0 } TEXT 1056, 0, 0 { PAGEALIGN 10 TEXT "Title:" RECT (1141,1444,1212,1497) ALIGN 4 MARGINS (1,10) COLOR (0,0,0) FONT (12,0,0,700,0,0,0,"Arial") } TEXT 1057, 0, 0 { PAGEALIGN 10 OUTLINE 5,1, (0,0,0) TEXT "$TITLE" RECT (1310,1440,1980,1500) ALIGN 4 MARGINS (1,1) COLOR (0,0,0) FONT (12,0,0,700,0,128,0,"Arial") UPDATE 0 } LINE 1058, 0, 0 { PAGEALIGN 10 OUTLINE 0,1, (128,128,128) POINTS ( (1130,1380), (2000,1380) ) FILL (1,(0,0,0),0) } LINE 1059, 0, 0 { PAGEALIGN 10 OUTLINE 0,1, (128,128,128) POINTS ( (1130,1440), (2000,1440) ) FILL (1,(0,0,0),0) } LINE 1060, 0, 0 { PAGEALIGN 10 OUTLINE 0,1, (128,128,128) POINTS ( (1300,1380), (1300,1500) ) } LINE 1061, 0, 0 { PAGEALIGN 10 OUTLINE 0,1, (128,128,128) POINTS ( (2000,1500), (2000,1240), (1130,1240), (1130,1500), (2000,1500) ) FILL (1,(0,0,0),0) } TEXT 1062, 0, 0 { PAGEALIGN 10 TEXT "(C)ALDEC. Inc\n"+ "2260 Corporate Circle\n"+ "Henderson, NV 89074" RECT (1140,1260,1435,1361) MARGINS (1,1) COLOR (0,0,0) FONT (12,0,0,700,0,0,0,"Arial") MULTILINE } LINE 1063, 0, 0 { PAGEALIGN 10 OUTLINE 0,1, (128,128,128) POINTS ( (1440,1240), (1440,1380) ) } LINE 1064, 0, 0 { PAGEALIGN 10 OUTLINE 0,4, (0,4,255) POINTS ( (1616,1304), (1682,1304) ) FILL (0,(0,4,255),0) } LINE 1065, 0, 0 { PAGEALIGN 10 OUTLINE 0,1, (0,4,255) POINTS ( (1585,1300), (1585,1300) ) FILL (0,(0,4,255),0) } LINE 1066, 0, 0 { PAGEALIGN 10 OUTLINE 0,3, (0,4,255) POINTS ( (1634,1304), (1650,1264) ) FILL (0,(0,4,255),0) } TEXT 1067, -4, 0 { PAGEALIGN 10 OUTLINE 5,0, (49,101,255) TEXT "ALDEC" RECT (1663,1246,1961,1348) MARGINS (1,1) COLOR (0,4,255) FONT (36,0,0,700,0,0,0,"Arial") } LINE 1068, 0, 0 { PAGEALIGN 10 OUTLINE 0,3, (0,4,255) POINTS ( (1576,1264), (1551,1327) ) FILL (0,(0,4,255),0) } BEZIER 1069, 0, 0 { PAGEALIGN 10 OUTLINE 0,3, (0,4,255) FILL (0,(0,4,255),0) ORIGINS ( (1583,1290), (1616,1304), (1583,1315), (1583,1290) ) CONTROLS (( (1607,1290), (1615,1289)),( (1613,1315), (1610,1315)),( (1583,1307), (1583,1302)) ) } LINE 1070, 0, 0 { PAGEALIGN 10 OUTLINE 0,4, (0,4,255) POINTS ( (1495,1311), (1583,1311) ) FILL (0,(0,4,255),0) } LINE 1071, 0, 0 { PAGEALIGN 10 OUTLINE 0,4, (0,4,255) POINTS ( (1502,1294), (1583,1294) ) FILL (0,(0,4,255),0) } LINE 1072, 0, 0 { PAGEALIGN 10 OUTLINE 0,1, (0,4,255) POINTS ( (1688,1271), (1511,1271) ) FILL (0,(0,4,255),0) } LINE 1073, 0, 0 { PAGEALIGN 10 OUTLINE 0,1, (0,4,255) POINTS ( (1686,1278), (1508,1278) ) FILL (0,(0,4,255),0) } LINE 1074, 0, 0 { PAGEALIGN 10 OUTLINE 0,1, (0,4,255) POINTS ( (1700,1286), (1506,1286) ) FILL (0,(0,4,255),0) } LINE 1075, 0, 0 { PAGEALIGN 10 OUTLINE 0,1, (0,4,255) POINTS ( (1702,1294), (1510,1294) ) FILL (0,(0,4,255),0) } LINE 1076, 0, 0 { PAGEALIGN 10 OUTLINE 0,1, (0,4,255) POINTS ( (1615,1302), (1499,1302) ) FILL (0,(0,4,255),0) } LINE 1077, 0, 0 { PAGEALIGN 10 OUTLINE 0,1, (0,4,255) POINTS ( (1680,1311), (1495,1311) ) FILL (0,(0,4,255),0) } LINE 1078, 0, 0 { PAGEALIGN 10 OUTLINE 0,1, (0,4,255) POINTS ( (1673,1319), (1492,1319) ) FILL (0,(0,4,255),0) } TEXT 1079, 0, 0 { PAGEALIGN 10 TEXT "The Design Verification Company" RECT (1482,1336,1934,1370) MARGINS (1,1) COLOR (0,4,255) FONT (12,0,0,700,1,0,0,"Arial") } LINE 1080, 0, 0 { PAGEALIGN 10 OUTLINE 0,1, (0,4,255) POINTS ( (1667,1327), (1489,1327) ) FILL (0,(0,4,255),0) } LINE 1081, 0, 0 { PAGEALIGN 10 OUTLINE 0,1, (0,4,255) POINTS ( (1690,1264), (1514,1264) ) FILL (0,(0,4,255),0) } } }