// // Title : 4 bit carry-lookahead unit test fixture // Design : Homework 5 // Author : Carl Ebeling // Company : CSE 370 // //------------------------------------------------------------------------------------------------- // // File : cla4_tf.v // // Description : This test fixture tests the 4-bit CLA component of the // carry-lookahead adder //------------------------------------------------------------------------------------------------- `timescale 1ns / 1ns module cla4_tf (cin, p, g, c, BP, BG); output cin; // Carry into block output [3:0] p, g; // Propagate and generate input signals input [3:0] c; // Carry outputs of CLA input BP, BG; // Block propagate and generate signals for next level reg cin; // Carry into block reg [3:0] p, g; // Propagate and generate input signals integer errors; integer count; integer i, good; reg [3:0] cRes; reg BPres, BGres; initial begin errors = 0; // Perform exhaustive test: for (count = 0; count < (1<<9); count = count + 1) begin { p, g, cin } = count; // Test vector #10 cRes[0] = cin; cRes[1] = g[0] | cin&p[0]; cRes[2] = g[1] | g[0]&p[1] | cin&p[1]&p[0]; cRes[3] = g[2] | g[1]&p[2] | g[0]&p[2]&p[1] | cin&p[2]&p[1]&p[0]; BPres = p[3]&p[2]&p[1]&p[0]; BGres = g[3] | g[2]&p[3] | g[1]&p[3]&p[2] | g[0]&p[3]&p[2]&p[1]; if ((cRes !== c) || (BPres != BP) || (BGres != BG)) begin $display("***Error*** p:%b, g:%b, cin:%b, c:%b, BP:%b, BG:%b", p, g, cin, c, BP, BG); $display(" should be c:%b, BP:%b, BG:%b", cRes, BPres, BGres); errors = errors + 1; $stop; end end if (errors == 0) $display("Test passed - No errors!!"); else $display("**** %d Errors****", errors); end endmodule