//-------------------------------------------------------------------------------------------------- // // Title : addsub32_tf // Design : // Author : // Company : // //------------------------------------------------------------------------------------------------- // // File : test_fixture.v // Generated : Wed Aug 14 09:03:05 2002 // From : interface description file // By : Itf2Vhdl ver. 1.20 // //------------------------------------------------------------------------------------------------- // // Description : This test fixture takes input from a 4-bit Ripple Add or Subtract and compares the sum from // adder with the expected sum. Additionally, it accepts an overflow input and signals // when an overflow occurs. // // Note: negative numbers will be printed to the screen in decimal form, therefore, // they may appear incorrect but this will not affect comparisons (i.e. -1 will print // to the screen as 15 since it will interpret the twos compliment version of 1111 as // a decimal 15) of the sum generated by the adder since the output is equivalent to // the twos compliment of the decimal number entered into the code below. If this // seems confusing, change all of the %d symbols to %b, and this will print the binary // version of the numbers to the screen instead of the decimal. // //------------------------------------------------------------------------------------------------- `timescale 1ns / 1ns module addsub32_tf ( A ,B ,AddSub ,Overflow ,Sum ); input Overflow ; wire Overflow ; input [31:0] Sum ; wire [31:0] Sum ; output [31:0] A ; reg [31:0] A ; output [31:0] B ; reg [31:0] B ; output AddSub; reg AddSub; integer results; integer i, errors, sumout, ovout; initial begin errors = 0; results = $fopen("addsub32_tf_output.txt"); if (results == 0) begin $display("Error: Unable to open file."); $finish; end results = results | 1; for (i = 0; i < 100; i=i+1) begin A = $random; B = $random; AddSub = $random; if (!AddSub) begin sumout = A + B; ovout = (A[31]&B[31]&~sumout[31]) || (~A[31]&~B[31]&sumout[31]); end else begin sumout = A - B; ovout = (A[31]&~B[31]&~sumout[31]) || (~A[31]&B[31]&sumout[31]); end $fdisplay(2, "A:%h, B:%h, AddSub:%d, sumout:%h, ovout:%d", A, B, AddSub, sumout, ovout); #70 if ((Sum!=sumout) || (Overflow!=ovout)) begin errors = errors + 1; $fdisplay(results, "Error: A=%d, B=%d, AddSub:%d, Sum=%d, Overflow=%d", A, B, AddSub, Sum, Overflow); end end if (errors > 0) begin $fdisplay(results, "%d Errors Found", errors); end else begin $fdisplay(results, "Test succeeded!!"); end end endmodule