/* README for AWESOME INFORMATION: * As the lab pointed out this clock divider takes the really fast * 24 MHz clock and slows it down. It does so with a little counter * which you can see inside the always block. Essentially instead of * raising and dropping the clock signal every tick, it waits a certain * number of ticks depending on how big you made period. * * Now, the lab mentions that the Enable Pulse Width needs to be 450ns. * To do the math you should figure out how long a period in a 24MHz * clock is. So, how many 24MHz ticks go by in 450ns? * * Once you have that number, all that's left is to double it. We double * it because 450ns is only the width of the high part of the pulse we need * the 450ns which represents the low part of the pulse for the full period. * * e.g.: _____450ns_____|-----450ns-----| */ module Clock_Divider (output reg clk, input fpga_clk); parameter period = // Fill in this constant, e.g. 16 reg [4:0] counter; initial begin counter = 0; clk = 0; end always @(posedge fpga_clk) begin if (counter == (period / 2) - 1) begin clk = !clk; counter = 0; end else begin counter = counter + 1; end end endmodule