CSE370 Goals & Syllabus

### Catalog Data

CSE370 Introduction to Digital Design (4) Introductory course in digital logic and its specification and simulation. Boolean algebra, combinatorial circuits including arithmetic circuits and regular structures, sequential circuits including finite-state machines, use of programmable logic devices. Simulation and high-level specification techniques are emphasized. Offered: AWSp.

The department has an official syllabus description for CSE 370

### Course Goals

1. Understanding of digital logic at the gate and switch level including both combinational and sequential logic elements.
2. Understanding of the clocking methodologies necessary to manage the flow of information and preservation of circuit state.
3. An appreciation for the specification methods used in designing digital logic and the basics of the compilation process that transforms these specifications into logic networks.
4. Facility with a complete set of tools for digital logic design with programmable logic devices as the implementation technology and the realization of medium-sized state machine controller and data paths using PLDs and discrete logic.
5. To begin to appreciate the difference between hardware and software implementations of a function and the advantages and disadvantages of each.
6. Understand “how” these concepts are used in the real world and “why” it is useful for us to know.

### Course Syllabus

1. Combinational logic basics
• Binary/hex/decimal numbers
• Ones and twos complement arithmetic
• Truth tables
• Boolean algebra
• Basic logic gates
• Schematic diagrams
• Timing diagrams
• De Morgan’s theorem
• AND/OR to NAND/NOR logic conversion
• K-maps (up to 4 variables), logic minimization, don’t cares
• SOP, POS
• Minterm and maxterm expansions (canonical, minimized)

2.      Combinational logic applications

• Combinational design

·         Input/output encoding

·         Truth table

·         K-map

·         Boolean equation

·         Schematics

o    Multiplexers/demultiplexers

o    PLAs/PALs

o    ROMs

1. Sequential logic building blocks
• Latches (R-S and D)
• Flip-flops (D and T)
• Latch and flip-flop timing (setup/hold time, prop delay)
• Timing diagrams
• Asynchronous inputs and metastability
• Registers

4.      Counters

• Timing diagrams
• Shift registers
• Ring counters
• State diagrams and state-transition tables
• Counter design procedure

1.       Draw a state diagram

2.       Draw a state-transition table

3.       Encode the next-state functions

4.       Implement the design

• Self-starting counters
1. Finite state machines
• Timing diagrams (synchronous FSMs)
• Moore versus Mealy versus synchronized Mealy
• FSM design procedure

1.       State diagram

2.       State-transition table

3.       State minimization

4.       State encoding

5.       Next-state logic minimization

6.       Implement the design

• State minimization
• One-hot / output-oriented encoding
• FSM design guidelines
• Pipelining, retiming partitioning basics