module Clock_Divider (output clk, input fpga_clk);
	//You need to modify the bits here to slow the clock down.
	parameter bits = x;
	//This bit of code creates a register with size specified
	reg [bits-1:0] counter;
	//This outputs a clock pulse when the very last bit is filled in the register.
	assign clk = counter[bits-1];
	//This starts the register at 0
	initial counter = 0;
	//This increments the counter 1 for every clock cycle, counting up. Eventually
	//last bit will be filled and a pulse will be went over clk. Then the counter
	//will cycle around back to 0.
	always @(posedge fpga_clk) counter = counter + 1;
endmodule