1. F(A,B,C,D) = Σm(0,4,5,6,7,9,11,13,14)
   Minimum cover:
   
   Hazard-free cover:
   
   
   
   
2. Let's name the outputs of the first XOR gate and NAND gate X and Y, respectively.

   A B	X Y F G
   0 0  0 1  1 0  1 1	0 1 1 1  1 1 1 0  1 1 0 0  0 0 1 0

   
   
   
   
   
3. 
   
   One of the many possible longest-delay paths is highlighted in red
   
   

   	Size	Delay
   Carry-Select	28 Full adders + 14 2-1 Muxes (or 15, if you count the last one)	4*delay(FA) + 3*delay(Mux)
   Ripple-Carry	16 Full adders	16*delay(FA)