module mux(a, b, sel, out);
        input a, b, sel;
        output out;
        assign out = sel ? a : b;
      endmodule
    

      module mux(a, b, sel, out);
        input a, b, sel;
        output out;
        reg out;
        always @ (a or b or sel) begin
          if (sel)
            out = a;
          else
            out = b;
        end
      endmodule
    

      module mux(a, b, sel, out);
        input a, b, sel;
        output out;
        wire selnot, as, bs;
        not (selnot, sel);
        and (as, a, sel);
        and (bs, b, selnot);
        or (out, as, bs);
      endmodule
    

      module full_adder(a, b, cin, s, cout);
        input a, b, cin;
        output s, cout;
        assign {cout, s} = a + b + cin;
      endmodule
    

      module adder2(a, b, o);
        input [1:0] a, b;
        output [1:0] o;
        wire [2:0] carry;

        assign carry[0] = 0;
        full_adder fa0(a[0], b[0], carry[0], o[0], carry[1]);
        full_adder fa1(a[1], b[1], carry[1], o[1], carry[2]);
      endmodule