Homework 3

Distributed Thursday, October 11, 2007
Due before 10:30, Wednesday, October 17, 2007

Please put your full name and lab section letter on your homework.

Always remember to staple your work, if it is multiple pieces of paper.

If you choose, indicate on the top of your assignment roughly how much time you spent on it. This information will have no impact on your grade; it will only be used by an inexperienced course staff to gauge the volume of work to assign.
  1. Reduce to min number of product terms using Boolean cube method:
    F(x,y,z) = Σm (1, 2, 4, 5) ( 10 points )
    [ Boolean cube minimization is just like K-map minimization, except you find planes in the cube instead of rectangles in the K-map. The concepts are perfectly analogous. ]

    For exercises 2-5, Use K-maps to find minimum 2-level implementations and draw the corresponding circuit. If an exercise asks you to use specific gates or a specific form (sum-of-products or product-of-sums), do so. Otherwise, you can choose whichever you prefer.
  2. 2.22 (c); and implement minimized F using only NAND gates and minimized F' using only NOR gate (5+5+5=15 points)
  3. Design a combinational circuit that detects an error in the representation of a decimal digit in BCD. The output of the circuit must be equal to logic 1 when the inputs contain any one of the six unused bit combinations in the BCD code. (10 points)
  4. Design a combinational circuit that multiplies 2, 2-bit numbers (A1 A0 and B1 B0). The four outputs are the four bits of the resulting product (P3 P2 P1 P0). (20 points)
  5. Minimize the following functions using K-maps:
    1. F(w,x,y,z) = ΠM(1,4,5,7,13)ΠD(9,14,15)     Use a sum-of-products style, and use only NOR gates.
    2. F(w,x,y,z) = Σm(1,3,5,8,9,12)+Σd(6,10,14)     Use a product-of-sums style, and use only NAND gates.
    (20 points)

    For the Verilog exercises, you can use whatever method you want to implement the functions. They need not be in minimized 2-level form (but they can be).
  6. Write a Verilog module that implements a 2-1 multiplexer (see figure 4.12 in the textbook for a truth table for a 2-1 multiplexer). (10 points)
  7. Write a Verilog module that implements a full adder. Use this module to build a two bit adder, with two 2-bit inputs A and B, and a 2-bit output O. (15 points)