The multiplication will take half as many clock cycles, but the critical path through the multiplier logic is approximately twice as long: (roughly) two adders instead of one. Therefore, if we are able to run at the maximum possible clock rate in both cases, the total time is about the same. This multiplier has substantially larger logic, though, so seems like a less good design. This design might be preferable if the clock period has to be long because of some other circuit that this one is put in a system with. That would make the number of clock cycles advantage important.
- R0 is 0
- R1 is 1
- R2 is 100
- R3 is 200
1: Load A R2
2: ReadMem
3: Load R4 Mem
4: Load A R0
5: Load B R4
6: Add
7: Load R0 Alu
8: Load A R2
9: Load B R1
10: Add
11: Load R2 Alu
12: Load A R2
13: Load B R3
14: LessThan #2
15: Done
1: Load A R0
2: Load B R1
3: GreaterThan #6
4: Load A R1
5: Load B R0
6: Subtract
7: Load R2 Alu
8: Done
| A En | T1 T2 T3 T4 T5 T6 Output |
| 0 0 0 1 1 0 1 1 |
C O O C O O Z O C C C O C 1 C O O O C O Z O C C O C C 0 |
