Homework 6

Distributed Thursday, November 1, 2007
Due before 10:30, Wednesday, November 7, 2007

Please put your full name and lab section letter on your homework.

Always remember to staple your work, if it is multiple pieces of paper.

If you choose, indicate on the top of your assignment roughly how much time you spent on it. This information will have no impact on your grade; it will only be used by an inexperienced course staff to gauge the volume of work to assign.
  1. (15 points)
    6.1.
  2. (15 points)
    6.10 (a,c,d[Assume the latch "remembers" when Clk=0 and passes its input when Clk=1]).
  3. (20 points)
    6.15. Note that flip-flops always implicitly have a clock input.
    Here is an example set of waves for a rising-edge triggered T flip-flop that happens to start with its output equal to 0. This is just provided to help you understand the behavior of the T flip-flop better.

    For the next three exercises, use this FPGA template. You can implement each circuit on a different template, or try to fit them all in one. Make sure you clearly label what each input and output is, and what each LUT is for, if you do more than one exercise on a single template.
  4. (15 points)
    Implement the following two functions on an FPGA template:
    1. F(A,B,C) = (A + B)(~B + C)(~A + ~B)
    2. G(A,B,C,D) = CD + ABC + A~B~C
  5. (15 points)
    Implement a 2-bit 2's complement adder on an FPGA template. The adder should have the usual 2-bit sum output and an overflow output, indicating when the result of the addition is too large or small to fit in two bits.
  6. (20 points)
    Implement a 4-bit shift register with the following characteristics on an FPGA template. The circuit will have a 1-bit data input, a 1-bit shift up input and a 1-bit shift down input. It will store four bits of data in registers and the output of the circuit is the values of these registers, o0, o1, o2 and o3. Since this circuit has registers, it must also have a clock input, but the clock is left entirely implicit in our FPGA template. If the shift up input is true, then the data in the registers "shifts up": o1 gets whatever o0 had, o2 gets whatever o1 had, and o3 gets whatever o2 had. The new value of o0 is determined by the value of the data input. If shift up is false and shift down is true, then the exact opposite shift happens: o2 gets whatever o3 had, o1 gets whatever o2 had, o0 gets whatever o1 had, and o3 gets the value of the data input. If both shift up and shift down are false, then all of the registers should keep the value that they currently have. In the FPGA template, the boxes with the triangles are simple D flip-flops, where the D input is connected to the LUT output, the Q output is connected to the wire that extends to the right, and the clock input is implicit.

    You may find it useful, both for thinking through the exercise and partial credit to draw a schematic before going to the FPGA template.