Exam 2 will cover course material up through the sequential Verilog lecture. The exercises on the exam will be similar to what you have seem on homework, so looking over you homeworks again is one of the most efficient ways you can prepare for the exam.

The topics covered since the last exam:

• Quine-McCluskey minimization. We have probably had enough Quine-McCluskey for now.
• Multi-level circuit design. This is covered in section 2.6, 2.7 and 3.3. 3.3 was never assigned, so any exercises related to multi-level circuit optimization will be relatively simple.
• Combinational circuit timing and glitches. This is one of the more important topics in 370 for the purpose of convincing you that hardware is different from software.
• Adders, comparators, ALUs. We didn't actually talk about ALUs, so don't worry if you don't know what that acronym stands for. You should be comfortable with adders, subtracters and comparators, though.
• Stateful primitives: latches and flip-flops.
• Guts of FPGAs. Knowing how to program the internal bits of FPGAs is not what I would call an essential core skill. We did it just to give you as clear of a picture as possible of what's going on inside.
• Timing of latches and registers; setup time, hold time, propagation delay.
• Finite state machine design (not implementation)
• Basic sequential Verilog