CSE370 Assignment 5

Distributed: 1 February 2006
Due: 8 February 2006

  1. Katz/Borriello, Contemporary Logic Design 2e, p 238-246, 259-277


  1. CLD-II, Chapter 4, problem 4.26 parts a,c,d (do b, don't submit)
  2. The ripple carry design for an adder in Tutorial #2 is effective, but slow because of the long chain of carry gates. A carry-lookahead adder addresses this problem by computing the carry-in for later gates in parallel with the sums. In this problem you will construct a 16-bit carry-lookahead adder.

    a) Design and test a 1-bit adder that has 3 inputs, A, B, Cin and three outputs: Sum, P, and G. P and G are the propogate and generate functions accordingly, and are defined in the following way: G = AB, P = A xor B. You may do this either with Verilog or a schematic

    b) Using your 1-bit adder, design and test a 4-bit adder component which has three input busses, A[3:0], B[3:0], Cin[3:0] and three output busses, Sum[3:0], P[3:0] and G[3:0]. (This 4-bit adder is just four independent copies of the 1-bit adder.) You must use a schematic for this.

    c) Design and test a 4-bit carry-lookahead component that has three inputs, P[3:0], G[3:0], Cin, and three outputs, Cout[3:0], BlockP, and BlockG. BlockP and BlockG are the block propagate and block generate functions. You must use a schematic for this.

    d) Using your 4-bit adder component and 4-bit carry-lookahead component, design and test a 16-bit carry-lookahead adder. You must use a schematic for this.

    e) What is the size (# of gates) and delay of your 16-bit carry-lookahead adder?

    f) If you continued and made a 64-bit carry-lookahead adder using these components, what would be the size and delay of that circuit?

    Turn-in your implementations/console outputs for part c,d and the answers to part e,f.

  3. The circuit you designed for part a of problem 1 is commonly called a carry-save adder. Produce a block diagram that takes 8 16-bit numbers as input and produces a single 16-bit output that is the sum of all 8 numbers. Assume that overflow will not occur.


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